Add Xh3bextm extension from Hazard3

1 files changed, 33 insertions, 1 deletions

diff --git a/rvcontroller.lua b/rvcontroller.lua
index 2370906..1e60474 100644
--- a/rvcontroller.lua
+++ b/rvcontroller.lua
@@ -7,7 +7,7 @@
 
 Emulated system specifications:
 
-Single RISC-V core, RV32IMACBZicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbkb_Zbkx instruction set, switchable endianness (little-endian default)
+Single RISC-V core, RV32IMACBZicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbkb_Zbkx_Xh3bextm instruction set, switchable endianness (little-endian default)
 65536 bytes of RAM (configurable in settings below) starting at base address 0
 
 Intended to be compliant with the following specifications:
@@ -48,6 +48,8 @@ Intended to be compliant with the following specifications:
 * "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01
 * Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0
 * Zbkx: Extension for Crossbar permutations, Version 1.0.0
+* Xh3bextm: Hazard3 bit extract multiple
+	- Note: Defined in the Hazard3 reference manual, available at https://github.com/Wren6991/Hazard3/releases/download/v1.1/hazard3.pdf
 
 See https://docs.riscv.org/reference/isa/unpriv/unpriv-index.html for full specifications.
 
@@ -1696,6 +1698,24 @@ local operations = {
 		mem.rswaiting = "sto"
 		return false,true
 	end,
+	h3bextm = function(rd,rs1,rs2,size)
+		local bits = explodebits(getreg(rs1),32)
+		local shamt = getreg(rs2)
+		local outbits = {}
+		for i=0,size-1 do
+			outbits[i] = bits[i+shamt] --May be nil if out of bounds but that's OK
+		end
+		setreg(rd,implodebits(outbits,32))
+	end,
+	h3bextmi = function(rd,rs1,rs2,size)
+		local bits = explodebits(getreg(rs1),32)
+		local shamt = rs2 --Register number field actually contains an immediate here
+		local outbits = {}
+		for i=0,size-1 do
+			outbits[i] = bits[i+shamt] --May be nil if out of bounds but that's OK
+		end
+		setreg(rd,implodebits(outbits,32))
+	end,
 }
 
 local function runinst(instruction)
@@ -2117,6 +2137,18 @@ local function runinst(instruction)
 			--pause
 			return false,true
 		end
+	elseif opcode == 0x0b then
+		--Custom instruction (currently all R-type)
+		local f3 = implodebits({[0] = bits[12],bits[13],bits[14]},3)
+		local xh3bextmsize = implodebits({[0] = bits[26],bits[27],bits[28]},3)+1
+		local rd = implodebits({[0] = bits[7],bits[8],bits[9],bits[10],bits[11]},5)
+		local rs1 = implodebits({[0] = bits[15],bits[16],bits[17],bits[18],bits[19]},5)
+		local rs2 = implodebits({[0] = bits[20],bits[21],bits[22],bits[23],bits[24]},5)
+		if f3 == 0 then
+			operations.h3bextm(rd,rs1,rs2,xh3bextmsize)
+		elseif f3 == 4 then
+			operations.h3bextmi(rd,rs1,rs2,xh3bextmsize)
+		end
 	else
 		mem.running = false
 		digiline_send("monitordisp",string.format("Invalid opcode %02X,\nhalted",opcode))