Add Xh3bextm extension from Hazard3

7 files changed, 101 insertions, 1 deletions

diff --git a/assembly/xh3bextm-test/Makefile b/assembly/xh3bextm-test/Makefile
new file mode 100644
index 0000000..62a1190
--- /dev/null
+++ b/assembly/xh3bextm-test/Makefile
@@ -0,0 +1,24 @@
+MARCH ?= rv32imacbzicntr_zicond_zicsr_zifencei_zihintpause_zilsd_zclsd_zabha_zacas_zbkb_zbkx_zcb_zcmp_zcmt
+
+.PHONY: all dump load clean
+
+all: xh3bextm-test.hex
+
+xh3bextm-test.o: xh3bextm-test.S
+	riscv32-none-elf-as -I../rvcontroller-libraries -march=${MARCH} -o xh3bextm-test.o xh3bextm-test.S
+
+xh3bextm-test.elf:  xh3bextm-test.o
+	riscv32-none-elf-ld -T rvcontroller.ld --no-warn-rwx-segments -o xh3bextm-test.elf xh3bextm-test.o
+
+dump: xh3bextm-test.elf
+	riscv32-none-elf-objdump -d xh3bextm-test.elf
+
+xh3bextm-test.hex: xh3bextm-test.elf
+	riscv32-none-elf-objcopy -O ihex xh3bextm-test.elf xh3bextm-test.hex
+
+load: xh3bextm-test.hex
+	bash -c "wl-copy < xh3bextm-test.hex"
+
+clean:
+	rm -f xh3bextm-test.bin xh3bextm-test.elf xh3bextm-test.o
+
diff --git a/assembly/xh3bextm-test/rvcontroller.ld b/assembly/xh3bextm-test/rvcontroller.ld
new file mode 120000
index 0000000..bc01402
--- /dev/null
+++ b/assembly/xh3bextm-test/rvcontroller.ld
@@ -0,0 +1 @@
+../../rvcontroller.ld
\ No newline at end of file
diff --git a/assembly/xh3bextm-test/xh3bextm-test.S b/assembly/xh3bextm-test/xh3bextm-test.S
new file mode 100644
index 0000000..20ae6c2
--- /dev/null
+++ b/assembly/xh3bextm-test/xh3bextm-test.S
@@ -0,0 +1,40 @@
+# Xh3bextm macros are from the Hazard3 reference manual, slightly modified
+.macro h3.bextm rd rs1 rs2 nbits
+	.if (\nbits < 1) || (\nbits > 8)
+		.err
+	.endif
+	.insn r 0x0b, 0x0, (((\nbits - 1) & 0x7 ) << 1), \rd, \rs1, \rs2
+.endm
+
+.macro h3.bextmi rd rs1 shamt nbits
+	.if (\nbits < 1) || (\nbits > 8)
+		.err
+	.endif
+	.if (\shamt < 0) || (\shamt > 31)
+		.err
+	.endif
+	.insn i 0x0b, 0x4, \rd, \rs1, (\shamt & 0x1f) | (((\nbits - 1) & 0x7 ) << 6)
+.endm
+
+li t0,0xdeadbeef
+li t1,4
+
+h3.bextm s0,t0,t1,6
+
+# 0xDEADBEEF = 1101 1110 1010 1101 1011 1110 1110 1111   (rs1)
+#                                         vv vvvv
+#                                         10 1110 = 0x2E
+#                                        |---6---|       (imm)
+#                                                |--4-|  (rs2)
+
+
+h3.bextmi s1,t0,16,3
+
+# 0xDEADBEEF = 1101 1110 1010 1101 1011 1110 1110 1111   (rs1)
+#                              vvv
+#                              101 = 0x5
+#                             |-3-|                      (imm2)
+#                                 |--------16--------|   (imm1)
+
+li a7,10
+ecall
diff --git a/assembly/xh3bextm-test/xh3bextm-test.elf b/assembly/xh3bextm-test/xh3bextm-test.elf
new file mode 100755
index 0000000..b0c4daa
--- /dev/null
+++ b/assembly/xh3bextm-test/xh3bextm-test.elf
diff --git a/assembly/xh3bextm-test/xh3bextm-test.hex b/assembly/xh3bextm-test/xh3bextm-test.hex
new file mode 100644
index 0000000..d52c119
--- /dev/null
+++ b/assembly/xh3bextm-test/xh3bextm-test.hex
@@ -0,0 +1,3 @@
+:10000000B7C2ADDE9382F2EE11430B8462148BC44F

+:080010000209A9487300000079

+:00000001FF

diff --git a/assembly/xh3bextm-test/xh3bextm-test.o b/assembly/xh3bextm-test/xh3bextm-test.o
new file mode 100644
index 0000000..99fbe2d
--- /dev/null
+++ b/assembly/xh3bextm-test/xh3bextm-test.o
diff --git a/rvcontroller.lua b/rvcontroller.lua
index 2370906..1e60474 100644
--- a/rvcontroller.lua
+++ b/rvcontroller.lua
@@ -7,7 +7,7 @@
 
 Emulated system specifications:
 
-Single RISC-V core, RV32IMACBZicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbkb_Zbkx instruction set, switchable endianness (little-endian default)
+Single RISC-V core, RV32IMACBZicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbkb_Zbkx_Xh3bextm instruction set, switchable endianness (little-endian default)
 65536 bytes of RAM (configurable in settings below) starting at base address 0
 
 Intended to be compliant with the following specifications:
@@ -48,6 +48,8 @@ Intended to be compliant with the following specifications:
 * "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01
 * Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0
 * Zbkx: Extension for Crossbar permutations, Version 1.0.0
+* Xh3bextm: Hazard3 bit extract multiple
+	- Note: Defined in the Hazard3 reference manual, available at https://github.com/Wren6991/Hazard3/releases/download/v1.1/hazard3.pdf
 
 See https://docs.riscv.org/reference/isa/unpriv/unpriv-index.html for full specifications.
 
@@ -1696,6 +1698,24 @@ local operations = {
 		mem.rswaiting = "sto"
 		return false,true
 	end,
+	h3bextm = function(rd,rs1,rs2,size)
+		local bits = explodebits(getreg(rs1),32)
+		local shamt = getreg(rs2)
+		local outbits = {}
+		for i=0,size-1 do
+			outbits[i] = bits[i+shamt] --May be nil if out of bounds but that's OK
+		end
+		setreg(rd,implodebits(outbits,32))
+	end,
+	h3bextmi = function(rd,rs1,rs2,size)
+		local bits = explodebits(getreg(rs1),32)
+		local shamt = rs2 --Register number field actually contains an immediate here
+		local outbits = {}
+		for i=0,size-1 do
+			outbits[i] = bits[i+shamt] --May be nil if out of bounds but that's OK
+		end
+		setreg(rd,implodebits(outbits,32))
+	end,
 }
 
 local function runinst(instruction)
@@ -2117,6 +2137,18 @@ local function runinst(instruction)
 			--pause
 			return false,true
 		end
+	elseif opcode == 0x0b then
+		--Custom instruction (currently all R-type)
+		local f3 = implodebits({[0] = bits[12],bits[13],bits[14]},3)
+		local xh3bextmsize = implodebits({[0] = bits[26],bits[27],bits[28]},3)+1
+		local rd = implodebits({[0] = bits[7],bits[8],bits[9],bits[10],bits[11]},5)
+		local rs1 = implodebits({[0] = bits[15],bits[16],bits[17],bits[18],bits[19]},5)
+		local rs2 = implodebits({[0] = bits[20],bits[21],bits[22],bits[23],bits[24]},5)
+		if f3 == 0 then
+			operations.h3bextm(rd,rs1,rs2,xh3bextmsize)
+		elseif f3 == 4 then
+			operations.h3bextmi(rd,rs1,rs2,xh3bextmsize)
+		end
 	else
 		mem.running = false
 		digiline_send("monitordisp",string.format("Invalid opcode %02X,\nhalted",opcode))