Add luacheck

1 files changed, 57 insertions, 34 deletions

diff --git a/rvcontroller.lua b/rvcontroller.lua
index ba03ea4..ef1985f 100644
--- a/rvcontroller.lua
+++ b/rvcontroller.lua
@@ -326,15 +326,15 @@ local function writeram(address,data,bytes,fake)
 				local bits = explodebits(mem.csr[0xc81],32)
 				local newbits = explodebits(thisbyte,8)
 				byteindex = byteindex - 4
-				for i=0,7 do
-					bits[byteindex*8+i] = newbits[i]
+				for bit=0,7 do
+					bits[byteindex*8+bit] = newbits[bit]
 				end
 				mem.csr[0xc81] = implodebits(bits,32)
 			else
 				local bits = explodebits(os.time()-mem.starttime,32)
 				local newbits = explodebits(thisbyte,8)
-				for i=0,7 do
-					bits[byteindex*8+i] = newbits[i]
+				for bit=0,7 do
+					bits[byteindex*8+bit] = newbits[bit]
 				end
 				local newmtime = implodebits(bits,32)
 				mem.starttime = os.time()-newmtime
@@ -347,15 +347,15 @@ local function writeram(address,data,bytes,fake)
 				local bits = explodebits(mem.mtimecmphigh,32)
 				local newbits = explodebits(thisbyte,8)
 				byteindex = byteindex - 4
-				for i=0,7 do
-					bits[byteindex*8+i] = newbits[i]
+				for bit=0,7 do
+					bits[byteindex*8+bit] = newbits[bit]
 				end
 				mem.mtimecmphigh = implodebits(bits,32)
 			else
 				local bits = explodebits(mem.mtimecmplow,32)
 				local newbits = explodebits(thisbyte,8)
-				for i=0,7 do
-					bits[byteindex*8+i] = newbits[i]
+				for bit=0,7 do
+					bits[byteindex*8+bit] = newbits[bit]
 				end
 				mem.mtimecmplow = implodebits(bits,32)
 			end
@@ -371,7 +371,7 @@ local stdoutdirty = false
 
 local function scrollstdout(lines)
 	lines = lines or 1
-	for i=1,lines do
+	for _=1,lines do
 		table.remove(mem.stdout,1)
 		mem.stdout[6] = ""
 	end
@@ -462,7 +462,8 @@ local function writecsr(address,data)
 		--misa
 		local bits = explodebits(data,32)
 		if mem.registers.pc % 4 == 2 and not bits[2] then
-			digiline_send("monitordisp",string.format("Attempted to disable\nC extension but\ninstruction would be\nmisaligned,\nwrite ignored\nPC: %08X",mem.registers.pc))
+			local msg = "Attempted to disable\nC extension but\ninstruction would be\nmisaligned,\nwrite ignored\nPC: %08X"
+			digiline_send("monitordisp",string.format(msg,mem.registers.pc))
 		end
 		mem.isa.a = bits[0]
 		mem.isa.b = bits[1]
@@ -523,9 +524,13 @@ local function trap(reason,val)
 		mem.mdt = true
 		if mem.trapmode == 1 then
 			--vectored mode
-			local int = reason >= 0x8000000
+			local int = reason >= 0x80000000
 			reason = reason%0x80000000
-			mem.registers.pc = reason*4+mem.trapbase
+			if int then
+				mem.registers.pc = reason*4+mem.trapbase
+			else
+				mem.registers.pc = mem.trapbase
+			end
 			return true,false
 		else
 			--direct or reserved (treated as direct) mode
@@ -817,7 +822,6 @@ local operations = {
 		local immbits = explodebits(imm,21)
 		signextend(immbits,21,32)
 		imm = implodebits(immbits,32,true)
-		local oldpc = mem.registers.pc
 		mem.registers.pc = (mem.registers.pc + imm) % 2^32
 		return true
 	end,
@@ -1226,7 +1230,7 @@ local operations = {
 		local num = getreg(rs1)
 		local amount = getreg(rs2)%32
 		if amount == 0 then return end
-		for i=1,amount do
+		for _=1,amount do
 			local endbit = num >= 2^31
 			num = (num*2)%2^32
 			if endbit then num = num + 1 end
@@ -1376,7 +1380,7 @@ local operations = {
 		end
 		setreg(rd,out)
 	end,
-	lr = function(rd,rs1,rs2)
+	lr = function(rd,rs1)
 		local address = getreg(rs1)
 		setreg(rd,readram(address,4))
 		mem.reservationset = address
@@ -1722,7 +1726,7 @@ local operations = {
 		local highhalf = (getreg(rs2)%2^8)*2^8
 		setreg(rd,lowhalf+highhalf)
 	end,
-	brev8 = function(rd,rs1,imm)
+	brev8 = function(rd,rs1)
 		local bits = explodebits(getreg(rs1),32)
 		local newbits = {}
 		for byte=0,3 do
@@ -1734,7 +1738,7 @@ local operations = {
 		end
 		setreg(rd,implodebits(newbits,32))
 	end,
-	zip = function(rd,rs1,imm)
+	zip = function(rd,rs1)
 		local bits = explodebits(getreg(rs1),32)
 		local newbits = {}
 		for i=0,15 do
@@ -1743,7 +1747,7 @@ local operations = {
 		end
 		setreg(rd,implodebits(newbits,32))
 	end,
-	unzip = function(rd,rs1,imm)
+	unzip = function(rd,rs1)
 		local bits = explodebits(getreg(rs1),32)
 		local newbits = {}
 		for i=0,15 do
@@ -1766,22 +1770,22 @@ local operations = {
 			setreg(rd,getreg(rs1))
 		end
 	end,
-	mopr = function(rd,rs1,imm)
+	mopr = function(rd)
 		setreg(rd,0)
 	end,
-	moprr = function(rd,rs1,rs2,imm)
+	moprr = function(rd)
 		setreg(rd,0)
 	end,
-	cmop = function(rd,imm)
+	cmop = function()
 		--Does nothing until/unless redefined by another extension
 	end,
-	wrsnto = function(rd,rs1)
+	wrsnto = function()
 		mem.rswaiting = "nto"
 		mem.running = false
 		digiline_send("monitordisp","Waiting for\nreservation set")
 		return false,true
 	end,
-	wrssto = function(rd,rs1)
+	wrssto = function()
 		mem.rswaiting = "sto"
 		return false,true
 	end,
@@ -2034,11 +2038,9 @@ local function runinst(instruction)
 			elseif f3 == 0x3 then
 				operations.csrrc(rd,rs1,imm)
 			elseif f3 == 0x4 and bits[31] and bits[24] and bits[23] and bits[22] and not (bits[29] or bits[28] or bits[25]) then
-				local immbits = implodebits({[0] = bits[20],bits[21],bits[26],bits[27],bits[30]},5)
-				operations.mopr(rd,rs1,imm)
+				operations.mopr(rd)
 			elseif f3 == 0x4 and bits[31] and bits[25] and not (bits[28] or bits[29]) then
-				local immbits = implodebits({[0] = bits[26],bits[27],bits[30]},3)
-				operations.moprr(rd,rs1,rs2,imm)
+				operations.moprr(rd)
 			elseif f3 == 0x5 then
 				operations.csrrwi(rd,rs1,imm)
 			elseif f3 == 0x6 then
@@ -2114,7 +2116,29 @@ local function runinst(instruction)
 		local rdbits = {[0] = bits[7],bits[8],bits[9],bits[10],bits[11]}
 		local rd = implodebits(rdbits,5)
 		--Something had to give after how easy the U-type immediates were
-		local immbits = {[0] = false,bits[21],bits[22],bits[23],bits[24],bits[25],bits[26],bits[27],bits[28],bits[29],bits[30],bits[20],bits[12],bits[13],bits[14],bits[15],bits[16],bits[17],bits[18],bits[19],bits[31]}
+		local immbits = {
+			[0] = false,
+			bits[21],
+			bits[22],
+			bits[23],
+			bits[24],
+			bits[25],
+			bits[26],
+			bits[27],
+			bits[28],
+			bits[29],
+			bits[30],
+			bits[20],
+			bits[12],
+			bits[13],
+			bits[14],
+			bits[15],
+			bits[16],
+			bits[17],
+			bits[18],
+			bits[19],
+			bits[31]
+		}
 		local imm = implodebits(immbits,21)
 		return operations.jal(rd,imm)
 	elseif opcode == 0x2f and mem.isa.a then
@@ -2401,9 +2425,9 @@ local function runcinst(instruction)
 		elseif imm ~= 0 then
 			--c.lui (CI)
 			signextend(immbits,6,20)
-			local imm = implodebits(immbits,20)
-			imm = imm*2^12
-			operations.lui(rd,imm)
+			local realimm = implodebits(immbits,20)
+			realimm = realimm*2^12
+			operations.lui(rd,realimm)
 		elseif rd%2 == 1 and rd <= 15 then
 			--c.mop
 			operations.cmop(rd,imm)
@@ -2527,7 +2551,7 @@ local function runcinst(instruction)
 		--This one decodes into possibly a whole bunch of instructions
 		local rlist = cmpushpopreglists[implodebits({[0] = bits[4],bits[5],bits[6],bits[7]},4)]
 		if not rlist then return end
-		stack = implodebits({[0] = bits[2],bits[3]},2) * 16 + rlist.stack
+		local stack = implodebits({[0] = bits[2],bits[3]},2) * 16 + rlist.stack
 		for i,reg in ipairs(rlist.registers) do
 			operations.sw(2,reg,-4*i)
 		end
@@ -2537,7 +2561,7 @@ local function runcinst(instruction)
 		--This one decodes into possibly a whole bunch of instructions
 		local rlist = cmpushpopreglists[implodebits({[0] = bits[4],bits[5],bits[6],bits[7]},4)]
 		if not rlist then return end
-		stack = implodebits({[0] = bits[2],bits[3]},2) * 16 + rlist.stack
+		local stack = implodebits({[0] = bits[2],bits[3]},2) * 16 + rlist.stack
 		operations.addi(2,2,stack)
 		for i,reg in ipairs(rlist.registers) do
 			operations.lw(reg,2,-4*i)
@@ -3198,5 +3222,4 @@ end
 if stdoutdirty then
 	local text = table.concat(mem.stdout,"\n")
 	digiline_send("stdout",text.."\n")
-	stdoutdirty = false
 end