RVController Instruction List
=============================

This file lists all supported instructions, grouped by extension.
Note that instruction descriptions may not exactly match official names, where applicable,
however the function of the instruction is the same.

RV32I Base Integer Instruction Set, Version 2.1:
* add rd,rs1,rs2        | Add register+register
* sub rd,rs1,rs2        | Subtract register-register
* xor rd,rs1,rs2        | Bitwise XOR register^register
* or rd,rs1,rs2         | Bitwise OR register|register
* and rd,rs1,rs2        | Bitwise AND register&register
* sll rd,rs1,rs2        | Shift left register<<register
* srl rd,rs1,rs2        | Logical shift right register>>register
* sra rd,rs1,rs2        | Arithmetic shift right register>>register
* slt rd,rs1,rs2        | Set if register<register
* sltu rd,rs1,rs2       | Set if register<register (unsigned)
* addi rd,rs1,imm       | Add register+immediate
* xori rd,rs1,imm       | Bitwise XOR register^immediate
* ori rd,rs1,imm        | Bitwise OR register|immediate
* andi rd,rs1,imm       | Bitwise AND register&immediate
* slli rd,rs1,imm       | Shift left register<<immediate
* srli rd,rs1,imm       | Shift right logical register>>immediate
* srai rd,rs1,imm       | Shift right arithmetic register>>immediate
* slti rd,rs1,imm       | Set if register<immediate
* stliu rd,rs1,imm      | Set if register<immediate (unsigned)
* lb rd,imm(rs1)        | Load byte
* lh rd,imm(rs1)        | Load halfword
* lw rd,imm(rs1)        | Load word
* lbu rd,imm(rs1)       | Load byte (unsigned)
* lhu rd,imm(rs1)       | Load halfword (unsigned)
* sb rs2,imm(rs1)       | Store byte
* sh rs2,imm(rs1)       | Store halfword
* sw rs2,imm(rs1)       | Store word
* beq rs1,rs2,imm       | Branch if register==register
* bne rs1,rs2,imm       | Branch if register!=register
* blt rs1,rs2,imm       | Branch if register<register
* bge rs1,rs2,imm       | Branch if register>=register
* bltu rs1,rs2,imm      | Branch if register<register (unsigned)
* bgeu rs1,rs2,imm      | Branch if register>=register (unsigned)
* jal rd,imm            | Jump to immediate and link
* jalr rd,rs1,imm       | Jump to register+immediate and link
* lui rd,imm            | Load upper immediate
* auipc rd,imm          | Add upper immediate to program counter
* ecall                 | Environment call
* ebreak                | Breakpoint
* fence                 | Memory / I/O fence

"M" Extension for Integer Multiplication and Division, Version 2.0:
* mul rd,rs1,rs2        | Multiply register*register (lower 32 bits)
* mulh rd,rs1,rs2       | Multiply register*register (signed*signed, upper 32 bits)
* mulhsu rd,rs1,rs2     | Multiply register*register (signed*unsigned, upper 32 bits)
* mulhu rd,rs1,rs2      | Multiply register*register (unsigned*unsigned, upper 32 bits)
* div rd,rs1,rs2        | Divide register/register (signed)
* divu rd,rs1,rs2       | Divide register/register (unsigned)
* rem rd,rs1,rs2        | Modulo register%register (signed)
* remu rd,rs1,rs2       | Modulo register%register (unsigned)

"A" Extension for Atomic Instructions, Version 2.1:
* lr.w rd,imm(rs1)      | Load word reserved
* sc.w rs2,imm(rs1)     | Store word conditional
* amoswap.w rd,rs1,rs2  | Atomic swap memory<->register, word size
* amoadd.w rd,rs1,rs2   | Atomic add memory+register, word size
* amoand.w rd,rs1,rs2   | Atomic bitwise AND memory&register, word size
* amoor.w rd,rs1,rs2    | Atomic bitwise OR memory|register, word size
* amoxor.w rd,rs1,rs2   | Atomic bitwise XOR memory^register, word size
* amomax.w rd,rs1,rs2   | Atomic integer maximum(memory,register), word size
* amomaxu.w rd,rs1,rs2  | Atomic integer maximum(memory,register) (unsigned), word size
* amomin.w rd,rs1,rs2   | Atomic integer minimum(memory,register), word size
* amominu.w rd,rs1,rs2  | Atomic integer minimum(memory,register) (unsigned), word size

"C" Extension for Compressed Instructions, Version 2.0
* c.lwsp rd,imm         | Compressed load word, stack pointer relative
* c.swsp rs2,imm        | Compressed store word, stack pointer relative
* c.lw rd,imm(rs1)      | Compressed load word
* c.sw rs2,imm(rs1)     | Compressed store word
* c.j imm               | Compressed jump
* c.jal imm             | Compressed jump and link
* c.jr rs1              | Compressed jump to register
* c.jalr rs1            | Compressed jump to register and link
* c.beqz rs1,imm        | Compressed branch if register==0
* c.bnez rs1,imm        | Compressed branch if register!=0
* c.li rd,imm           | Compressed load immediate
* c.lui rd,imm          | Compressed load upper immediate
* c.addi rd,imm         | Compressed add immediate
* c.addi16sp imm        | Compressed add immediate*16 to stack pointer
* c.addi4spn rd,imm     | Compressed add immediate*4 + stack pointer
* c.slli rd,imm         | Compressed shift left by immediate
* c.srli rd,imm         | Compressed logical shift right by immediate
* c.srai rd,imm         | Compressed arithmetic shift right by immediate
* c.andi rd,imm         | Compressed bitwise AND with immediate
* c.mv rd,rs2           | Compressed move
* c.add rd,rs2          | Compressed add
* c.and rd,rs2          | Compressed bitwise AND
* c.or rd,rs2           | Compressed bitwise OR
* c.xor rd,rs2          | Compressed bitwise XOR
* c.sub rd,rs2          | Compressed subtract
* c.nop                 | Compressed no operation
* c.ebreak              | Compressed breakpoint

"B" Extension for Bit Manipulation, Version 1.0.0
* sh1add rd,rs1,rs2     | Shift left by 1 and add
* sh2add rd,rs1,rs2     | Shift left by 2 and add
* sh3add rd,rs1,rs2     | Shift left by 3 and add
* andn rd,rs1,rs2       | Bitwise AND with inverted operand
* orn rd,rs1,rs2        | Bitwise OR with inverted operand
* xnor rd,rs1,rs2       | Bitwise XNOR
* clz rd,rs1            | Count leading zero bits
* ctz rd,rs1            | Count trailing zero bits
* cpop rd,rs1           | Count set bits
* max rd,rs1,rs2        | Signed integer maximum
* maxu rd,rs1,rs2       | Unsigned integer maximum
* min rd,rs1,rs2        | Signed integer minimum
* minu rd,rs1,rs2       | Unsigned integer minimum
* sext.b rd,rs1         | Sign-extend byte
* sext.h rd,rs1         | Sign-extend halfword
* rol rd,rs1,rs2        | Rotate left by register
* ror rd,rs1,rs2        | Rotate right by register
* rori rd,rs1,rs2       | Rotate right by immediate
* orc.b rd,rs1          | Bitwise OR-combine, byte granule
* rev8 rd,rs1           | Byte-reverse register
* bclr rd,rs1,rs2       | Single-bit clear (by register)
* bclri rd,rs1,imm      | Single-bit clear (by immediate)
* bext rd,rs1,rs2       | Single-bit extract (by register)
* bexti rd,rs1,rs2      | Single-bit extract (by immediate)
* binv rd,rs1,rs2       | Single-bit invert (by register)
* binvi rd,rs1,rs2      | Single-bit invert (by immediate)
* bset rd,rs1,rs2       | Single-bit set (by register)
* bseti rd,rs1,rs2      | Single-bit set (by immediate)

Zicfilp: Control Flow Integrity - Landing Pad:
* lpad imm              | Landing pad

"Zicond" Extension for Integer Conditional Operations, Version 1.0.0
* czero.eqz rd,rs1,rs2  | Conditional zero, if condition==0
* czero.nez rd,rs1,rs2  | Conditional zero, if condition!=0

"Zicsr" Extension for Control and Status Register (CSR) Instructions, Version 2.0
* csrrw rd,csr,rs1      | Atomic read/write register to CSR
* csrrwi rd,csr,imm     | Atomic read/write immediate to CSR
* csrrs rd,csr,rs1      | Atomic read/set bits by register in CSR
* csrrsi rd,csr,imm     | Atomic read/set bits by immediate in CSR
* csrrc rd,csr,rs1      | Atomic read/clear bits by register in CSR
* csrrci rd,csr,imm     | Atomic read/clear bits by immediate in CSR

"Zifencei" Extension for Instruction-Fetch Fence, Version 2.0
* fence.i               | Instruction-fetch fence

"Zihintpause" Extension for Pause Hint, Version 2.0
* pause                 | Pause hint

Zilsd, Zclsd: Extensions for Load/Store pair for RV32, Version 1.0
* ld rd,imm(rs1)        | Load doubleword
* sd rs2,imm(rs1)       | Store doubleword
* c.ldsp rd,imm         | Compressed load doubleword, stack pointer relative
* c.sdsp rd,imm         | Compressed store doubleword, stack pointer relative
* c.ld rd,imm(rs1)      | Compressed load doubleword
* c.sd rs2,imm(rs1)     | Compressed store doubleword

"Zimop" Extension for May-Be-Operations, Version 1.0
* mop.r.1 rd,rs1        | May-be-operation, R type, 1
* mop.r.2 rd,rs1        | May-be-operation, R type, 2
* mop.r.3 rd,rs1        | May-be-operation, R type, 3
* mop.r.4 rd,rs1        | May-be-operation, R type, 4
* mop.r.5 rd,rs1        | May-be-operation, R type, 5
* mop.r.6 rd,rs1        | May-be-operation, R type, 6
* mop.r.7 rd,rs1        | May-be-operation, R type, 7
* mop.r.8 rd,rs1        | May-be-operation, R type, 8
* mop.r.9 rd,rs1        | May-be-operation, R type, 9
* mop.r.10 rd,rs1       | May-be-operation, R type, 10
* mop.r.11 rd,rs1       | May-be-operation, R type, 11
* mop.r.12 rd,rs1       | May-be-operation, R type, 12
* mop.r.13 rd,rs1       | May-be-operation, R type, 13
* mop.r.14 rd,rs1       | May-be-operation, R type, 14
* mop.r.15 rd,rs1       | May-be-operation, R type, 15
* mop.r.16 rd,rs1       | May-be-operation, R type, 16
* mop.r.17 rd,rs1       | May-be-operation, R type, 17
* mop.r.18 rd,rs1       | May-be-operation, R type, 18
* mop.r.19 rd,rs1       | May-be-operation, R type, 19
* mop.r.20 rd,rs1       | May-be-operation, R type, 20
* mop.r.21 rd,rs1       | May-be-operation, R type, 21
* mop.r.22 rd,rs1       | May-be-operation, R type, 22
* mop.r.23 rd,rs1       | May-be-operation, R type, 23
* mop.r.24 rd,rs1       | May-be-operation, R type, 24
* mop.r.25 rd,rs1       | May-be-operation, R type, 25
* mop.r.26 rd,rs1       | May-be-operation, R type, 26
* mop.r.27 rd,rs1       | May-be-operation, R type, 27
* mop.r.28 rd,rs1       | May-be-operation, R type, 28
* mop.r.29 rd,rs1       | May-be-operation, R type, 29
* mop.r.30 rd,rs1       | May-be-operation, R type, 30
* mop.r.31 rd,rs1       | May-be-operation, R type, 31
* mop.r.32 rd,rs1       | May-be-operation, R type, 32
* mop.rr.1 rd,rs1,rs2   | May-be-operation, RR type, 1
* mop.rr.2 rd,rs1,rs2   | May-be-operation, RR type, 1
* mop.rr.3 rd,rs1,rs2   | May-be-operation, RR type, 1
* mop.rr.4 rd,rs1,rs2   | May-be-operation, RR type, 1
* mop.rr.5 rd,rs1,rs2   | May-be-operation, RR type, 1
* mop.rr.6 rd,rs1,rs2   | May-be-operation, RR type, 1
* mop.rr.7 rd,rs1,rs2   | May-be-operation, RR type, 1
* mop.rr.8 rd,rs1,rs2   | May-be-operation, RR type, 1

"Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0
* amoswap.h rd,rs1,rs2  | Atomic swap memory<->register, halfword size
* amoadd.h rd,rs1,rs2   | Atomic add memory+register, halfword size
* amoand.h rd,rs1,rs2   | Atomic bitwise AND memory&register, halfword size
* amoor.h rd,rs1,rs2    | Atomic bitwise OR memory|register, halfword size
* amoxor.h rd,rs1,rs2   | Atomic bitwise XOR memory^register, halfword size
* amomax.h rd,rs1,rs2   | Atomic integer maximum(memory,register), halfword size
* amomaxu.h rd,rs1,rs2  | Atomic integer maximum(memory,register) (unsigned), halfword size
* amomin.h rd,rs1,rs2   | Atomic integer minimum(memory,register), halfword size
* amominu.h rd,rs1,rs2  | Atomic integer minimum(memory,register) (unsigned), halfword size
* amocas.h rd,rs1,rs2   | Atomic compare-and-swap, halfword size
* amoswap.b rd,rs1,rs2  | Atomic swap memory<->register, byte size
* amoadd.b rd,rs1,rs2   | Atomic add memory+register, byte size
* amoand.b rd,rs1,rs2   | Atomic bitwise AND memory&register, byte size
* amoor.b rd,rs1,rs2    | Atomic bitwise OR memory|register, byte size
* amoxor.b rd,rs1,rs2   | Atomic bitwise XOR memory^register, byte size
* amomax.b rd,rs1,rs2   | Atomic integer maximum(memory,register), byte size
* amomaxu.b rd,rs1,rs2  | Atomic integer maximum(memory,register) (unsigned), byte size
* amomin.b rd,rs1,rs2   | Atomic integer minimum(memory,register), byte size
* amominu.b rd,rs1,rs2  | Atomic integer minimum(memory,register) (unsigned), byte size
* amocas.b rd,rs1,rs2   | Atomic compare-and-swap, byte size

"Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0
* amocas.w rd,rs1,rs2   | Atomic compare-and-swap, word size
* amocas.d rd,rs1,rs2   | Atomic compare-and-swap, doubleword size

"Zalasr" Atomic Load-Acquire and Store-Release Instructions, Version 1.0
* lb.aq rd,rs1          | Load-acquire byte
* lh.aq rd,rs1          | Load-acquire halfword
* lw.aq rd,rs1          | Load-acquire word
* lb.aqrl rd,rs1        | Load-acquire/release byte
* lh.aqrl rd,rs1        | Load-acquire/release halfword
* lw.aqrl rd,rs1        | Load-acquire/release word
* sb.rl rd,rs1          | Store-release byte
* sh.rl rd,rs1          | Store-release halfword
* sw.rl rd,rs1          | Store-release word
* sb.aqrl rd,rs1        | Store-acquire/release byte
* sh.aqrl rd,rs1        | Store-acquire/release halfword
* sw.aqrl rd,rs1        | Store-acquire/release word

"Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01
* wrs.nto               | Wait on reservation set, no timeout
* wrs.sto               | Wait on reservation set, short timeout

Zcb: Extension for Code Size Reduction, Version 1.0.0
* c.lbu rd,imm(rs1)     | Compressed load unsigned byte
* c.lhu rd,imm(rs1)     | Compressed load unsigned halfword
* c.lh rd,imm(rs1)      | Compressed load halfword
* c.sb rs2,imm(rs1)     | Compressed store byte
* c.sh rs2,imm(rs1)     | Compressed store halfword
* c.zext.b rd           | Compressed zero-extend byte
* c.sext.b rd           | Compressed sign-extend byte
* c.zext.h rd           | Compressed zero-extend halfword
* c.sext.h rd           | Compressed sign-extend halfword
* c.not rd              | Compressed bitwise NOT
* c.mul rd,rs2          | Compressed multiply

"Zcmop" Compressed May-Be-Operations Extension, Version 1.0
* c.mop.1               | Compressed may-be-operation 1
* c.mop.3               | Compressed may-be-operation 3
* c.mop.5               | Compressed may-be-operation 5
* c.mop.7               | Compressed may-be-operation 7
* c.mop.9               | Compressed may-be-operation 9
* c.mop.11              | Compressed may-be-operation 11
* c.mop.13              | Compressed may-be-operation 13
* c.mop.15              | Compressed may-be-operation 15

Zcmp: Extension for Code Size Reduction, Version 1.0.0
* cm.push {list},imm    | Compressed push register list
* cm.pop {list},imm     | Compressed pop register list
* cm.popret {list},imm  | Compressed pop register list and return
* cm.popretz {list},imm | Compressed pop register list and return 0
* cm.mva01s rs1,rs2     | Compressed move two s0-s7 registers into a0-a1
* cm.mvsa01 rd1,rd2     | Compressed move a0-a1 into two s0-s7 registers

Zcmt: Extension for Code Size Reduction, Version 1.0.0
* cm.jt imm             | Compressed jump via table
* cm.jalt imm           | Compressed jump via table and link

Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0
* pack rd,rs1,rs2       | Pack low halves
* packh rd,rs1,rs2      | Pack low bytes
* brev8 rd,rs1          | Reverse bits in bytes
* zip rd,rs1            | Interleave halves of register
* unzip rd,rs1          | Deinterleave halves of register

Zbkx: Extension for Crossbar permutations, Version 1.0.0
* xperm4 rd,rs1,rs2     | Crossbar permutation (nibbles)
* xperm8 rd,rs1,rs2     | Crossbar permutation (bytes)

Xh3bextm: Hazard3 bit extract multiple
* h3.bextm rd,rs1,rs2,imm    | Bit extract multiple, offset by register
* h3.bextmi rd,rs1,imm1,imm2 | Bit extract multiple, offset by immediate

Machine-Level ISA, Version 1.13
* mret                  | Return from M-mode trap
* wfi                   | Wait for interrupt
