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| author | cheapie <cheapiephp@gmail.com> | 2026-11-07 17:37:17 -0600 |
|---|---|---|
| committer | cheapie <cheapiephp@gmail.com> | 2026-11-07 17:37:17 -0600 |
| commit | a8711e74bbffda6a38fb5fea55bc96da6b8df41d (patch) | |
| tree | b412207dca2897419d57fda9979522cfbaa2a027 /doc | |
| parent | 9ae11c52355e8a362d34d7cabfbc573ddf8c2f80 (diff) | |
| download | rvcontroller-a8711e74bbffda6a38fb5fea55bc96da6b8df41d.tar rvcontroller-a8711e74bbffda6a38fb5fea55bc96da6b8df41d.tar.gz rvcontroller-a8711e74bbffda6a38fb5fea55bc96da6b8df41d.tar.bz2 rvcontroller-a8711e74bbffda6a38fb5fea55bc96da6b8df41d.tar.xz rvcontroller-a8711e74bbffda6a38fb5fea55bc96da6b8df41d.zip | |
Add Zksh
Wouldn't want China to feel left out
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/_start_here.txt | 5 | ||||
| -rw-r--r-- | doc/instructions.txt | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/doc/_start_here.txt b/doc/_start_here.txt index 0d06129..b2693d1 100644 --- a/doc/_start_here.txt +++ b/doc/_start_here.txt @@ -5,7 +5,7 @@ RVController is a program for use in Luacontrollers (from the mesecons mod) in L It emulates a single RISC-V hart and a configurable amount (64KiB default) of RAM. Features: -* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Zknh_Zkr_Xh3bextm_Xh3misa instruction set provides: +* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Zknh_Zkr_Zksh_Xh3bextm_Xh3misa instruction set provides: - 32-bit address space - 32 32-bit registers (31 general-purpose + 1 zero register) - Selectable endianness @@ -21,7 +21,7 @@ Features: - Single-instruction function prologues/epilogues and jump tables - Compatibility with future MOP-based extensions - Forward-edge control-flow integrity via landing pads - - SHA-256 and SHA-512 hash acceleration + - SHA-256, SHA-512, and SM3 hash acceleration - Compatibility with most code (not involving I/O) written for the WCH CH32V003, Espressif ESP32-C2/C3/C5/C6/C61/H2, Renesas R9A02G020/R9A02G021/R9A06G150, the RISC-V cores of the Raspberry Pi Pico 2, and many other chips * Mutable ISA via writable bits in misa CSR * Mesecons and digilines I/O @@ -81,6 +81,7 @@ RVController is intended to be compliant with the following specifications: * Zknh - NIST Suite: Hash Function, Version 1.0.1 * Zkr - Entropy Source Extension, Version 1.0.1 - Note: Virtual source, backed by Lua math.random(), 16 bits available per clock cycle +* Zksh - ShangMi Suite: SM3 Hash Function, Version 1.0.1 * Zicfilp: Control Flow Integrity - Landing Pad * Xh3misa: Hazard3 ISA identification register, Version 1.0 - Note: Defined in the Hazard3 reference manual, available at https://github.com/Wren6991/Hazard3/releases/download/v1.1/hazard3.pdf diff --git a/doc/instructions.txt b/doc/instructions.txt index b7a0b86..49d9147 100644 --- a/doc/instructions.txt +++ b/doc/instructions.txt @@ -310,6 +310,10 @@ Zknh - NIST Suite: Hash Function * sha512sum0r rd,rs1,rs2 | SHA2-512 Sum0 * sha512sum1r rd,rs1,rs2 | SHA2-512 Sum1 +Zksh - ShangMi Suite: SM3 Hash Function +* sm3p0 rd,rs1 | SM3 P0 transform +* sm3p1 rd,rs1 | SM3 P1 transform + Xh3bextm: Hazard3 bit extract multiple * h3.bextm rd,rs1,rs2,imm | Bit extract multiple, offset by register * h3.bextmi rd,rs1,imm1,imm2 | Bit extract multiple, offset by immediate |