diff options
| -rw-r--r-- | assembly/zkshtest/Makefile | 24 | ||||
| l--------- | assembly/zkshtest/rvcontroller.ld | 1 | ||||
| -rw-r--r-- | assembly/zkshtest/zkshtest.S | 22 | ||||
| -rw-r--r-- | doc/_start_here.txt | 5 | ||||
| -rw-r--r-- | doc/instructions.txt | 4 | ||||
| -rw-r--r-- | rvcontroller.lua | 32 |
6 files changed, 85 insertions, 3 deletions
diff --git a/assembly/zkshtest/Makefile b/assembly/zkshtest/Makefile new file mode 100644 index 0000000..bb2bff8 --- /dev/null +++ b/assembly/zkshtest/Makefile @@ -0,0 +1,24 @@ +MARCH ?= rv32imacbzicntr_zicond_zicsr_zifencei_zihintpause_zilsd_zclsd_zabha_zacas_zbkb_zbkx_zcb_zcmp_zcmt_zicboz_zknh_zksh + +.PHONY: all dump load clean + +all: zkshtest.hex + +zkshtest.o: zkshtest.S + riscv32-none-elf-as -I../rvcontroller-libraries -march=${MARCH} -o zkshtest.o zkshtest.S + +zkshtest.elf: zkshtest.o + riscv32-none-elf-ld -T rvcontroller.ld --no-warn-rwx-segments -o zkshtest.elf zkshtest.o + +dump: zkshtest.elf + riscv32-none-elf-objdump -d zkshtest.elf + +zkshtest.hex: zkshtest.elf + riscv32-none-elf-objcopy -O ihex zkshtest.elf zkshtest.hex + +load: zkshtest.hex + bash -c "wl-copy < zkshtest.hex" + +clean: + rm -f zkshtest.hex zkshtest.elf zkshtest.o + diff --git a/assembly/zkshtest/rvcontroller.ld b/assembly/zkshtest/rvcontroller.ld new file mode 120000 index 0000000..bc01402 --- /dev/null +++ b/assembly/zkshtest/rvcontroller.ld @@ -0,0 +1 @@ +../../rvcontroller.ld
\ No newline at end of file diff --git a/assembly/zkshtest/zkshtest.S b/assembly/zkshtest/zkshtest.S new file mode 100644 index 0000000..1bc78af --- /dev/null +++ b/assembly/zkshtest/zkshtest.S @@ -0,0 +1,22 @@ +li a0,0x12345678 + +sm3p0 s0,a0 + +rori t0,a0,(32-9) +xor s1,a0,t0 +rori t0,a0,(32-17) +xor s1,s1,t0 + + + +sm3p1 s2,a0 + +rori t0,a0,(32-15) +xor s3,a0,t0 +rori t0,a0,(32-23) +xor s3,s3,t0 + + + +li a7,10 +ecall diff --git a/doc/_start_here.txt b/doc/_start_here.txt index 0d06129..b2693d1 100644 --- a/doc/_start_here.txt +++ b/doc/_start_here.txt @@ -5,7 +5,7 @@ RVController is a program for use in Luacontrollers (from the mesecons mod) in L It emulates a single RISC-V hart and a configurable amount (64KiB default) of RAM. Features: -* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Zknh_Zkr_Xh3bextm_Xh3misa instruction set provides: +* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Zknh_Zkr_Zksh_Xh3bextm_Xh3misa instruction set provides: - 32-bit address space - 32 32-bit registers (31 general-purpose + 1 zero register) - Selectable endianness @@ -21,7 +21,7 @@ Features: - Single-instruction function prologues/epilogues and jump tables - Compatibility with future MOP-based extensions - Forward-edge control-flow integrity via landing pads - - SHA-256 and SHA-512 hash acceleration + - SHA-256, SHA-512, and SM3 hash acceleration - Compatibility with most code (not involving I/O) written for the WCH CH32V003, Espressif ESP32-C2/C3/C5/C6/C61/H2, Renesas R9A02G020/R9A02G021/R9A06G150, the RISC-V cores of the Raspberry Pi Pico 2, and many other chips * Mutable ISA via writable bits in misa CSR * Mesecons and digilines I/O @@ -81,6 +81,7 @@ RVController is intended to be compliant with the following specifications: * Zknh - NIST Suite: Hash Function, Version 1.0.1 * Zkr - Entropy Source Extension, Version 1.0.1 - Note: Virtual source, backed by Lua math.random(), 16 bits available per clock cycle +* Zksh - ShangMi Suite: SM3 Hash Function, Version 1.0.1 * Zicfilp: Control Flow Integrity - Landing Pad * Xh3misa: Hazard3 ISA identification register, Version 1.0 - Note: Defined in the Hazard3 reference manual, available at https://github.com/Wren6991/Hazard3/releases/download/v1.1/hazard3.pdf diff --git a/doc/instructions.txt b/doc/instructions.txt index b7a0b86..49d9147 100644 --- a/doc/instructions.txt +++ b/doc/instructions.txt @@ -310,6 +310,10 @@ Zknh - NIST Suite: Hash Function * sha512sum0r rd,rs1,rs2 | SHA2-512 Sum0 * sha512sum1r rd,rs1,rs2 | SHA2-512 Sum1 +Zksh - ShangMi Suite: SM3 Hash Function +* sm3p0 rd,rs1 | SM3 P0 transform +* sm3p1 rd,rs1 | SM3 P1 transform + Xh3bextm: Hazard3 bit extract multiple * h3.bextm rd,rs1,rs2,imm | Bit extract multiple, offset by register * h3.bextmi rd,rs1,imm1,imm2 | Bit extract multiple, offset by immediate diff --git a/rvcontroller.lua b/rvcontroller.lua index ee66cd3..459116d 100644 --- a/rvcontroller.lua +++ b/rvcontroller.lua @@ -485,7 +485,7 @@ local function readcsr(address) false, --Zkne true, --Zknh false, --Zksed - false, --Zksh + true, --Zksh true, --Zkt true, --Ztso false, --Zvbb @@ -2212,6 +2212,32 @@ local operations = { end setreg(rd,implodebits(outputbits,32)) end, + sm3p0 = function(rd,rs1) + local outputbits = {} + local function xor(index,new) + if new then outputbits[index] = not outputbits[index] end + end + local srcbits = explodebits(getreg(rs1),32) + for i=0,31 do + outputbits[i] = srcbits[i] + xor(i,srcbits[(i-9)%32]) + xor(i,srcbits[(i-17)%32]) + end + setreg(rd,implodebits(outputbits,32)) + end, + sm3p1 = function(rd,rs1) + local outputbits = {} + local function xor(index,new) + if new then outputbits[index] = not outputbits[index] end + end + local srcbits = explodebits(getreg(rs1),32) + for i=0,31 do + outputbits[i] = srcbits[i] + xor(i,srcbits[(i-15)%32]) + xor(i,srcbits[(i-23)%32]) + end + setreg(rd,implodebits(outputbits,32)) + end, } local function runinst(instruction) @@ -2364,6 +2390,10 @@ local function runinst(instruction) operations.sha256sig0(rd,rs1) elseif f3 == 0x1 and imm == 0x103 then operations.sha256sig1(rd,rs1) + elseif f3 == 0x1 and imm == 0x108 then + operations.sm3p0(rd,rs1) + elseif f3 == 0x1 and imm == 0x109 then + operations.sm3p1(rd,rs1) elseif f3 == 0x5 and math.floor(imm/0x20) == 0x0 then operations.srli(rd,rs1,imm%0x20) elseif f3 == 0x5 and math.floor(imm/0x20) == 0x20 then |