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| author | cheapie <cheapiephp@gmail.com> | 2026-11-07 08:38:37 -0600 |
|---|---|---|
| committer | cheapie <cheapiephp@gmail.com> | 2026-11-07 08:38:37 -0600 |
| commit | 15d38061302f61304e276f0045d8e4b3f1548e33 (patch) | |
| tree | 423f37df73b446fd16c951cfeb5cae91e44b8f7a /doc | |
| parent | b16ca179a848c470bc6719856106bafec5638963 (diff) | |
| download | rvcontroller-15d38061302f61304e276f0045d8e4b3f1548e33.tar rvcontroller-15d38061302f61304e276f0045d8e4b3f1548e33.tar.gz rvcontroller-15d38061302f61304e276f0045d8e4b3f1548e33.tar.bz2 rvcontroller-15d38061302f61304e276f0045d8e4b3f1548e33.tar.xz rvcontroller-15d38061302f61304e276f0045d8e4b3f1548e33.zip | |
Add Zkr
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/_start_here.txt | 4 | ||||
| -rw-r--r-- | doc/csr.txt | 1 |
2 files changed, 4 insertions, 1 deletions
diff --git a/doc/_start_here.txt b/doc/_start_here.txt index 745f83a..0ca3f65 100644 --- a/doc/_start_here.txt +++ b/doc/_start_here.txt @@ -5,7 +5,7 @@ RVController is a program for use in Luacontrollers (from the mesecons mod) in L It emulates a single RISC-V hart and a configurable amount (64KiB default) of RAM. Features: -* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Xh3bextm_Xh3misa instruction set provides: +* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Zkr_Xh3bextm_Xh3misa instruction set provides: - 32-bit address space - 32 32-bit registers (31 general-purpose + 1 zero register) - Selectable endianness @@ -77,6 +77,8 @@ RVController is intended to be compliant with the following specifications: * "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01 * Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0 * Zbkx: Extension for Crossbar permutations, Version 1.0.0 +* Zkr - Entropy Source Extension, Version 1.0.1 + - Note: Virtual source, backed by Lua math.random(), 16 bits available per clock cycle * Zicfilp: Control Flow Integrity - Landing Pad * Xh3misa: Hazard3 ISA identification register, Version 1.0 - Note: Defined in the Hazard3 reference manual, available at https://github.com/Wren6991/Hazard3/releases/download/v1.1/hazard3.pdf diff --git a/doc/csr.txt b/doc/csr.txt index 8c2c465..054fd9c 100644 --- a/doc/csr.txt +++ b/doc/csr.txt @@ -2,6 +2,7 @@ RVController Control and Status Registers ========================================= The following standard CSRs are available: +* 0x015: seed * 0x017: jvt * 0x300: mstatus * 0x301: misa (0x40801107 = RV32IMACBX) |