Add Zkr

6 files changed, 68 insertions, 3 deletions

diff --git a/assembly/zkrtest/Makefile b/assembly/zkrtest/Makefile
new file mode 100644
index 0000000..7cb4731
--- /dev/null
+++ b/assembly/zkrtest/Makefile
@@ -0,0 +1,24 @@
+MARCH ?= rv32imacbzicntr_zicond_zicsr_zifencei_zihintpause_zilsd_zclsd_zabha_zacas_zbkb_zbkx_zcb_zcmp_zcmt_zicboz_zkr
+
+.PHONY: all dump load clean
+
+all: zkrtest.hex
+
+zkrtest.o: zkrtest.S
+	riscv32-none-elf-as -I../rvcontroller-libraries -march=${MARCH} -o zkrtest.o zkrtest.S
+
+zkrtest.elf:  zkrtest.o
+	riscv32-none-elf-ld -T rvcontroller.ld --no-warn-rwx-segments -o zkrtest.elf zkrtest.o
+
+dump: zkrtest.elf
+	riscv32-none-elf-objdump -d zkrtest.elf
+
+zkrtest.hex: zkrtest.elf
+	riscv32-none-elf-objcopy -O ihex zkrtest.elf zkrtest.hex
+
+load: zkrtest.hex
+	bash -c "wl-copy < zkrtest.hex"
+
+clean:
+	rm -f zkrtest.hex zkrtest.elf zkrtest.o
+
diff --git a/assembly/zkrtest/rvcontroller.ld b/assembly/zkrtest/rvcontroller.ld
new file mode 120000
index 0000000..bc01402
--- /dev/null
+++ b/assembly/zkrtest/rvcontroller.ld
@@ -0,0 +1 @@
+../../rvcontroller.ld
\ No newline at end of file
diff --git a/assembly/zkrtest/zkrtest.S b/assembly/zkrtest/zkrtest.S
new file mode 100644
index 0000000..6fe98d5
--- /dev/null
+++ b/assembly/zkrtest/zkrtest.S
@@ -0,0 +1,11 @@
+csrrw s0,seed,x0
+csrrw s1,seed,x0
+pause
+csrrw s2,seed,x0
+csrrw s3,seed,x0
+pause
+
+csrrsi s4,seed,0 # This should crash
+
+li a7,10
+ecall
diff --git a/doc/_start_here.txt b/doc/_start_here.txt
index 745f83a..0ca3f65 100644
--- a/doc/_start_here.txt
+++ b/doc/_start_here.txt
@@ -5,7 +5,7 @@ RVController is a program for use in Luacontrollers (from the mesecons mod) in L
 It emulates a single RISC-V hart and a configurable amount (64KiB default) of RAM.
 
 Features:
-* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Xh3bextm_Xh3misa instruction set provides:
+* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Zkr_Xh3bextm_Xh3misa instruction set provides:
  - 32-bit address space
  - 32 32-bit registers (31 general-purpose + 1 zero register)
  - Selectable endianness
@@ -77,6 +77,8 @@ RVController is intended to be compliant with the following specifications:
 * "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01
 * Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0
 * Zbkx: Extension for Crossbar permutations, Version 1.0.0
+* Zkr - Entropy Source Extension, Version 1.0.1
+	- Note: Virtual source, backed by Lua math.random(), 16 bits available per clock cycle
 * Zicfilp: Control Flow Integrity - Landing Pad
 * Xh3misa: Hazard3 ISA identification register, Version 1.0
 	- Note: Defined in the Hazard3 reference manual, available at https://github.com/Wren6991/Hazard3/releases/download/v1.1/hazard3.pdf
diff --git a/doc/csr.txt b/doc/csr.txt
index 8c2c465..054fd9c 100644
--- a/doc/csr.txt
+++ b/doc/csr.txt
@@ -2,6 +2,7 @@ RVController Control and Status Registers
 =========================================
 
 The following standard CSRs are available:
+* 0x015: seed
 * 0x017: jvt
 * 0x300: mstatus
 * 0x301: misa (0x40801107 = RV32IMACBX)
diff --git a/rvcontroller.lua b/rvcontroller.lua
index 29dd903..8033a01 100644
--- a/rvcontroller.lua
+++ b/rvcontroller.lua
@@ -13,6 +13,8 @@ local CLOCK_SPEED = 20 --Clock speed in Hz when not in lightweight mode
 local INSTRUCTIONS_PER_CLOCK = 50 --Maximum number of instructions that will be run on each clock cycle
 local STDOUT_TO_TERMINAL = false --Whether to show standard output on the Luacontroller terminal in addition to the screen
 
+local seed = math.random(0,0xffff) + 0x80000000
+
 local traptypes = {
 	--Not all of these are implemented, some are impossible on RVController
 	[0x0] = "Inst addr misaligned",
@@ -398,7 +400,11 @@ local function stdout(text)
 end
 
 local function readcsr(address)
-	if address == 0x341 then --mepc
+	if address == 0x015 then --seed
+		local out = seed
+		seed = 0x40000000
+		return out
+	elseif address == 0x341 then --mepc
 		local ret = mem.csr[0x341]
 		--mepc[0] must be 0
 		if ret%2 == 1 then ret = ret-1 end
@@ -570,7 +576,10 @@ local function readcsr(address)
 end
 
 local function writecsr(address,data)
-	if address == 0x17 then
+	if address == 0x15 then
+		--seed
+		return
+	elseif address == 0x17 then
 		--jvt
 		data = math.floor(data/2^6)*2^6 --WARL, and mode is required to be 0
 	elseif address == 0xc00 or address == 0xc01 or address == 0xc02 or address == 0xc80 or address == 0xc81 or address == 0xc82 then
@@ -1181,6 +1190,10 @@ local operations = {
 	csrrs = function(rd,rs1,imm)
 		local out = readcsr(imm)
 		if rs1 == 0 then
+			if imm == 0x015 then
+				--Read-only access to seed
+				return trap(2)
+			end
 			setreg(rd,out)
 			return
 		end
@@ -1196,6 +1209,10 @@ local operations = {
 	csrrc = function(rd,rs1,imm)
 		local out = readcsr(imm)
 		if rs1 == 0 then
+			if imm == 0x015 then
+				--Read-only access to seed
+				return trap(2)
+			end
 			setreg(rd,out)
 			return
 		end
@@ -1220,6 +1237,10 @@ local operations = {
 		return checkinterrupts()
 	end,
 	csrrsi = function(rd,rs1,imm)
+		if getreg(rs1) == 0 and imm == 0x015 then
+			--Read-only access to seed
+			return trap(2)
+		end
 		setreg(rd,readcsr(imm))
 		if rs1 == 0 then return end
 		local csrbits = explodebits(readcsr(imm),32)
@@ -1231,6 +1252,10 @@ local operations = {
 		return checkinterrupts()
 	end,
 	csrrci = function(rd,rs1,imm)
+		if getreg(rs1) == 0 and imm == 0x015 then
+			--Read-only access to seed
+			return trap(2)
+		end
 		setreg(rd,readcsr(imm))
 		if rs1 == 0 then return end
 		local csrbits = explodebits(readcsr(imm),32)
@@ -2993,6 +3018,7 @@ local regaliases = {
 }
 
 local csraliases = {
+	seed = 0x015,
 	cycle = 0xc00,
 	time = 0xc01,
 	instret = 0xc02,