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Diffstat (limited to 'rvcontroller.lua')
| -rw-r--r-- | rvcontroller.lua | 216 |
1 files changed, 3 insertions, 213 deletions
diff --git a/rvcontroller.lua b/rvcontroller.lua index f3a85d2..ba03ea4 100644 --- a/rvcontroller.lua +++ b/rvcontroller.lua @@ -3,219 +3,9 @@ --This is free and unencumbered software released into the public domain. --See http://unlicense.org/ for more information ---[[ - -Emulated system specifications: - -Single RISC-V core, RV32IMACBZicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbkb_Zbkx_Xh3bextm instruction set, switchable endianness (little-endian default) -65536 bytes of RAM (configurable in settings below) starting at base address 0 - -Intended to be compliant with the following specifications: -* RV32I Base Integer Instruction Set, Version 2.1 -* "Zifencei" Extension for Instruction-Fetch Fence, Version 2.0 - - Note: Implemented as a 'nop' instruction as memory is always consistent (see note on RVWMO below) -* "Zicsr" Extension for Control and Status Register (CSR) Instructions, Version 2.0 -* "Zicond" Extension for Integer Conditional Operations, Version 1.0.0 -* "Zicntr" Extension for Counters, Version 2.0 -* "Zimop" Extension for May-Be-Operations, Version 1.0 -* "M" Extension for Integer Multiplication and Division, Version 2.0 - - Note: This implies the following: - - * Zmmul Extension, Version 1.0 -* "A" Extension for Atomic Instructions, Version 2.1 - - Note: This implies the following: - - * "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions - - * "Zaamo" Extension for Atomic Memory Operations -* RVWMO Memory Consistency Model, Version 2.0 - - Note: The actual implemented memory model is significantly more strict (memory is always consistent, there is no cache) -* "Ztso" Extension for Total Store Ordering, Version 1.0 -* "C" Extension for Compressed Instructions, Version 2.0 - - Note: This implies the following: - - * "Zca" Extension for Code Size Reduction, Version 1.0.0 -* Zcb: Extension for Code Size Reduction, Version 1.0.0 -* "Zcmop" Compressed May-Be-Operations Extension, Version 1.0 -* Zcmp: Extension for Code Size Reduction, Version 1.0.0 -* Zcmt: Extension for Code Size Reduction, Version 1.0.0 -* "B" Extension for Bit Manipulation, Version 1.0.0 - - Note: This implies the following: - - * Zba: Extension for Address generation, Version 1.0.0 - - * Zbb: Extension for Basic bit-manipulation, Version 1.0.0 - - * Zbs: Extension for Single-bit instructions, Version 1.0.0 -* "Zihintpause" Extension for Pause Hint, Version 2.0 -* Zilsd, Zclsd: Extensions for Load/Store pair for RV32, Version 1.0 -* "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 -* "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 -* "Zalasr" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 -* "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01 -* Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0 -* Zbkx: Extension for Crossbar permutations, Version 1.0.0 -* Zicfilp: Control Flow Integrity - Landing Pad -* Xh3bextm: Hazard3 bit extract multiple - - Note: Defined in the Hazard3 reference manual, available at https://github.com/Wren6991/Hazard3/releases/download/v1.1/hazard3.pdf -* Machine-Level ISA, Version 1.13 -* "Smdbltrp" Double Trap Extension, Version 1.0 - -See https://docs.riscv.org/reference/isa/unpriv/unpriv-index.html for full specifications. - -Monitor commands: - -peek <address> -Reads and displays the byte (8 bits) value from RAM at the specified address - -poke <address> <data> -Writes the specified byte (8 bits) value to RAM at the specified address - -peekw <address> -Reads and displays the word (32 bits) value from RAM starting at the specified address - -pokew <address> <data> -Writes the specified word (32 bits) value to RAM starting at the specified address - -getreg <register number> -Displays the current value of the specified register number (0-31) - -setreg <register number> <value> -Sets the specified register (0-31) to the specified value - -getpc -Displays the current value of the program counter - -setpc <value> -Sets the program counter to the specified value - -reset -Stops the CPU, resets all registers to zero, and clears all RAM - -step -Allows the CPU to run for one instruction, then halts - -run -Allows the CPU to run indefinitely - -stop -Halts the CPU - -setbreak <address> -Sets a breakpoint on the specified address. -Note that the breakpoint triggers just *before* the instruction fetch, -as in the instruction with the breakpoint on it will not have executed yet. -There can only be one breakpoint at a time. If one is already set, the new one will replace it. - -clearbreak -Clears any set breakpoint. Note that an ebreak instruction will still cause a break. - -help [command] -Shows information on a monitor command, or a list of commands if none is specified - - -ecall operations: - -NOTE: When in RV32E mode, replace a7 with a5. a5 can also be used in place of a7 in I mode if a7 is 0. - -a7 = 0 -Run the operation from the a5 register instead, unless a5 is also 0 in which case no operation occurs - -a7 = 1 -Prints the integer value from register a0 - -a7 = 4 -Prints the null-terminated string from the address specified by register a0 - -a7 = 5 -Reads an integer from the console and stores it into register a0 -This will block until the user enters a valid number - -a7 = 8 -Reads a string from the console and stores it (with a null terminator) into the address pointed to by register a0 -Will not read more than the length specified in register a1, anything more is discarded -This will block until the user types something - -a7 = 10 -Exits the program (halts the CPU) - -a7 = 11 -Prints the character stored in the register a0 - -a7 = 12 -Reads one character from the console (any more characters on the line are discarded) and stores it into register a0 - -a7 = 128 -Gets a random integer (between the values in registers a0 and a1) and stores it into register a0 - -a7 = 129 -Sends a digilines string message: -* channel is specified by the null-terminated string at the address specified by register a0 -* message is specified by the null-terminated string at the address specified by register a1 - -a7 = 130 -Gets the number of characters available to read from the console input buffer -Result is stored in register a0 - -a7 = 131 -Clears the console input buffer - -a7 = 132 -Reads one character from the console input buffer and stores it into register a0 -This will not block - if no data is available to read, a NUL character (0) is returned -The input buffer can store up to 256 characters - if full, incoming characters are dropped - -a7 = 133 -Gets the number of messages in the digilines receive buffer -Result is stored in register a0 - -a7 = 134 -Clears the digilines receive buffer - -a7 = 135 -Reads one message from the digilines receive buffer, returns channel and message as null-terminated strings -This will not block - if no data is available to read, zero-length strings will be returned -Arguments: -a0 - Address that the channel string will be written to -a1 - Size of the buffer that the channel string will be written into -a2 - Address that the message will be written to -a3 - Size of the buffer that the message will be written into - -Custom CSRs: - -0x800[0]: Lightweight mode, controls processor clock speed and behavior when mapblock is unloaded: -0: 10 Hz (adjustable in settings below), processor does not stop when mapblock is unloaded -1: 1 Hz, processor stops when mapblock is unloaded -Note that when set to 0, a digilines message being received will cause the processor to run for one cycle. -This is intended to be used to check if the digilines message needs action to be taken in response, -and the program can then turn lightweight mode off if so. - -0x801: MMIO Base Address (see MMIO section below) -May be set to any address with no alignment restrictions. -0 to disable, all other values enable. - -MMIO: - -Base address is selected by CSR 0x801 above. - -Base + 0: Mesecons I/O Direction -Format: [0000dcba] (WARL) -0 in the bit corresponding to an I/O pin selects input, 1 selects output. -Changing a pin from output to input while the output is active may cause unusual behavior due to Luacontroller limitations. - -Base + 1: Mesecons I/O Data -Format: [0000dcba] (Input bits are RO, output bits are RW) -For inputs: Each bit contains the state of the corresponding input. Writes are ignored. -For outputs: Each bit contains the state of the corresponding output. Writing to these bits turns the output on/off. - -Base + 2: mtime (see RISC-V Machine Level ISA specification) - -Base + 10: mtimecmp (see RISC-V Machine Level ISA specification) - -Base + 18 - Base + 255: Reserved - -Interrupts: - -Bits 7/16/17 of mie/mip are currently implemented. - -Bit 7: MTIP (machine timer interrupt), standard -Bit 16: MCIP (mesecons input interrupt), custom for RVController -Bit 17: DGIP (digilines receive interrupt), custom for RVController - -]] +--Documentation has moved to the "doc" directory in the repository. +--If you don't have a copy of this, you can find it here: +--https://cheapiesystems.com/git/rvcontroller/tree/doc --Settings local RAM_SIZE = 0x10000 --RAM size in bytes, must be a multiple of 256 |