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-rw-r--r--doc/_start_here.txt7
1 files changed, 5 insertions, 2 deletions
diff --git a/doc/_start_here.txt b/doc/_start_here.txt
index 125de5f..745f83a 100644
--- a/doc/_start_here.txt
+++ b/doc/_start_here.txt
@@ -5,12 +5,12 @@ RVController is a program for use in Luacontrollers (from the mesecons mod) in L
It emulates a single RISC-V hart and a configurable amount (64KiB default) of RAM.
Features:
-* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbkb_Zbkx_Xh3bextm_Xh3misa instruction set provides:
+* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Xh3bextm_Xh3misa instruction set provides:
- 32-bit address space
- 32 32-bit registers (31 general-purpose + 1 zero register)
- Selectable endianness
- Multiply/divide instructions
- - Bit manipulation including crossbar permutation and multiple-bit extraction
+ - Bit manipulation including crossbar permutation, multiple-bit extraction, and carry-less multiplication
- Atomic memory operations via load-reserved/store-conditional, compare-and-swap, or math/bitwise operations directly on memory
- Byte/halfword/word atomic memory operation sizes
- Conditional zero instructions
@@ -66,6 +66,9 @@ RVController is intended to be compliant with the following specifications:
- * Zba: Extension for Address generation, Version 1.0.0
- * Zbb: Extension for Basic bit-manipulation, Version 1.0.0
- * Zbs: Extension for Single-bit instructions, Version 1.0.0
+* Zbc: Extension for Carry-less multiplication, Version 1.0.0
+ - Note: This implies the following:
+ - * Zbkc: Extension for Carry-less multiplication for Cryptography, Version 1.0.0
* "Zihintpause" Extension for Pause Hint, Version 2.0
* Zilsd, Zclsd: Extensions for Load/Store pair for RV32, Version 1.0
* "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0