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| author | cheapie <cheapiephp@gmail.com> | 2026-11-07 05:45:09 -0600 |
|---|---|---|
| committer | cheapie <cheapiephp@gmail.com> | 2026-11-07 05:45:09 -0600 |
| commit | b6ecc5f2f1c6aa350b2fdb4d73b6bd410bdab951 (patch) | |
| tree | dd1932a4c5c7e050d67697dbc0d1af077c136716 /rvcontroller.lua | |
| parent | 69111aaf1a2b936bfa9d9ba53a4653f27c93312d (diff) | |
| download | rvcontroller-b6ecc5f2f1c6aa350b2fdb4d73b6bd410bdab951.tar rvcontroller-b6ecc5f2f1c6aa350b2fdb4d73b6bd410bdab951.tar.gz rvcontroller-b6ecc5f2f1c6aa350b2fdb4d73b6bd410bdab951.tar.bz2 rvcontroller-b6ecc5f2f1c6aa350b2fdb4d73b6bd410bdab951.tar.xz rvcontroller-b6ecc5f2f1c6aa350b2fdb4d73b6bd410bdab951.zip | |
Add Zbc (and by extension, Zbkc)
Diffstat (limited to 'rvcontroller.lua')
| -rw-r--r-- | rvcontroller.lua | 55 |
1 files changed, 53 insertions, 2 deletions
diff --git a/rvcontroller.lua b/rvcontroller.lua index 7d6a211..d7a93c6 100644 --- a/rvcontroller.lua +++ b/rvcontroller.lua @@ -459,9 +459,9 @@ local function readcsr(address) mem.isa.a, --Zacas mem.isa.b, --Zba mem.isa.b, --Zbb - false, --Zbc + mem.isa.b, --Zbc mem.isa.b, --Zbkb - false, --Zbkc + mem.isa.b, --Zbkc } return implodebits(bits,32) elseif page == 1 then @@ -1998,6 +1998,51 @@ local operations = { local segment = address/0x100 mem.ram[segment] = string.rep(string.char(0),256) end, + clmul = function(rd,rs1,rs2) + local outputbits = {} + local rs1bits = explodebits(getreg(rs1),32) + local rs2bits = explodebits(getreg(rs2),32) + for i=0,31 do + if rs2bits[i] then + for j=0,31 do + if rs1bits[j] then + outputbits[i+j] = not outputbits[i+j] + end + end + end + end + setreg(rd,implodebits(outputbits,32)) + end, + clmulh = function(rd,rs1,rs2) + local outputbits = {} + local rs1bits = explodebits(getreg(rs1),32) + local rs2bits = explodebits(getreg(rs2),32) + for i=0,31 do + if rs2bits[i] then + for j=0,31 do + if rs1bits[j] then + outputbits[i+j-32] = not outputbits[i+j-32] + end + end + end + end + setreg(rd,implodebits(outputbits,32)) + end, + clmulr = function(rd,rs1,rs2) + local outputbits = {} + local rs1bits = explodebits(getreg(rs1),32) + local rs2bits = explodebits(getreg(rs2),32) + for i=0,31 do + if rs2bits[31-i] then + for j=0,31 do + if rs1bits[j] then + outputbits[0-i+j] = not outputbits[0-i+j] + end + end + end + end + setreg(rd,implodebits(outputbits,32)) + end, } local function runinst(instruction) @@ -2066,6 +2111,12 @@ local function runinst(instruction) operations.orn(rd,rs1,rs2) elseif f3 == 0x4 and f7 == 0x20 and mem.isa.b then operations.xnor(rd,rs1,rs2) + elseif f3 == 0x1 and f7 == 0x5 and mem.isa.b then + operations.clmul(rd,rs1,rs2) + elseif f3 == 0x2 and f7 == 0x5 and mem.isa.b then + operations.clmulr(rd,rs1,rs2) + elseif f3 == 0x3 and f7 == 0x5 and mem.isa.b then + operations.clmulh(rd,rs1,rs2) elseif f3 == 0x6 and f7 == 0x5 then operations.max(rd,rs1,rs2) elseif f3 == 0x7 and f7 == 0x5 then |