Move documentation out of the program and into separate filesHEADmain

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+RVController Control and Status Registers
+=========================================
+
+The following standard CSRs are available:
+* 0x017: jvt
+* 0x300: mstatus
+* 0x301: misa (0x40801107 = RV32IMACBX)
+* 0x304: mie
+* 0x305: mtvec
+* 0x310: mstatush
+* 0x340: mscratch
+* 0x341: mepc
+* 0x342: mcause
+* 0x343: mtval
+* 0x344: mip
+* 0x34b: mtval2
+* 0x747: mseccfg
+* 0xb00: mcycle
+* 0xb02: minstret
+* 0xb80: mcycleh
+* 0xb82: minstreth
+* 0xc00: cycle
+* 0xc01: time
+* 0xc02: instret
+* 0xc80: cycleh
+* 0xc81: timeh
+* 0xc82: instreth
+* 0xf11: mvendorid (0)
+* 0xf12: marchid (53)
+* 0xf13: mimpid ("RVCo")
+* 0xf14: mhartid (0)
+
+The following custom CSRs are also available:
+
+0x800 - Clock Configuration
+
+ 31                                 1   0
++-----------------------------------------+
+|            Reserved                 | LW|
++-----------------------------------------+
+
+The LW field controls the type of interrupts used.
+* LW=0: Standard interrupts are used. The clock behavior does not depend on player location, and when running, the clock runs at the configured frequency.
+* LW=1: Lightweight interrupts are used. The clock stops when no players are nearby and restarts when a player is nearby again. The clock speed is always 1Hz.
+Lightweight interrupts require mooncontroller. If RVController is running on a mesecons Luacontroller, LW will only control the clock speed.
+
+0x801 - MMIO Base Address
+
+ 31                                      0
++-----------------------------------------+
+|               Address                   |
++-----------------------------------------+
+
+When set to a value in the range 0x00000001 - 0xffffff00,
+the Address field selects the base address of the 256-byte MMIO region.
+When set to 0x00000000, MMIO is disabled.
+See mmio.txt for MMIO region contents.
+
+Additionally, the mip and mie CSRs have some interrupts that are not yet implemented,
+while some of the platform-use bits have been assigned to additional interrupts.
+
+0x304 - mie (Machine Interrupt-Enable)
+
+ 31                       18   17   16   15     8    7   6           0
++---------------------------------------------------------------------+
+|          Reserved          |MDIE|MMIE| Reserved |MTIE|   Reserved   |
++---------------------------------------------------------------------+
+
+0x344 - mie (Machine Interrupt-Pending)
+
+ 31                       18   17   16   15     8    7   6           0
++---------------------------------------------------------------------+
+|          Reserved          |MDIP|MMIP| Reserved |MTIP|   Reserved   |
++---------------------------------------------------------------------+
+
+* MTIE/MTIP: Machine Timer Interrupt (see RISC-V Machine-Level ISA documentation)
+* MMIE/MMIP: Machine Mesecons Interrupt - Becomes pending when a mesecons input changes state and remains pending until manually set to 0
+* MDIE/MDIP: Machine Digilines Interrupt - Becomes pending when a digilines message is received and remains pending until manually set to 0