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| author | cheapie <cheapiephp@gmail.com> | 2026-11-07 16:25:42 -0600 |
|---|---|---|
| committer | cheapie <cheapiephp@gmail.com> | 2026-11-07 16:25:42 -0600 |
| commit | 9ae11c52355e8a362d34d7cabfbc573ddf8c2f80 (patch) | |
| tree | d5543de18e410daa4f0efbcec323d1ad7f8513c9 /doc/_start_here.txt | |
| parent | 15d38061302f61304e276f0045d8e4b3f1548e33 (diff) | |
| download | rvcontroller-9ae11c52355e8a362d34d7cabfbc573ddf8c2f80.tar rvcontroller-9ae11c52355e8a362d34d7cabfbc573ddf8c2f80.tar.gz rvcontroller-9ae11c52355e8a362d34d7cabfbc573ddf8c2f80.tar.bz2 rvcontroller-9ae11c52355e8a362d34d7cabfbc573ddf8c2f80.tar.xz rvcontroller-9ae11c52355e8a362d34d7cabfbc573ddf8c2f80.zip | |
Add Zknh
Diffstat (limited to 'doc/_start_here.txt')
| -rw-r--r-- | doc/_start_here.txt | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/doc/_start_here.txt b/doc/_start_here.txt index 0ca3f65..0d06129 100644 --- a/doc/_start_here.txt +++ b/doc/_start_here.txt @@ -5,7 +5,7 @@ RVController is a program for use in Luacontrollers (from the mesecons mod) in L It emulates a single RISC-V hart and a configurable amount (64KiB default) of RAM. Features: -* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Zkr_Xh3bextm_Xh3misa instruction set provides: +* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Zknh_Zkr_Xh3bextm_Xh3misa instruction set provides: - 32-bit address space - 32 32-bit registers (31 general-purpose + 1 zero register) - Selectable endianness @@ -21,6 +21,7 @@ Features: - Single-instruction function prologues/epilogues and jump tables - Compatibility with future MOP-based extensions - Forward-edge control-flow integrity via landing pads + - SHA-256 and SHA-512 hash acceleration - Compatibility with most code (not involving I/O) written for the WCH CH32V003, Espressif ESP32-C2/C3/C5/C6/C61/H2, Renesas R9A02G020/R9A02G021/R9A06G150, the RISC-V cores of the Raspberry Pi Pico 2, and many other chips * Mutable ISA via writable bits in misa CSR * Mesecons and digilines I/O @@ -77,6 +78,7 @@ RVController is intended to be compliant with the following specifications: * "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01 * Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0 * Zbkx: Extension for Crossbar permutations, Version 1.0.0 +* Zknh - NIST Suite: Hash Function, Version 1.0.1 * Zkr - Entropy Source Extension, Version 1.0.1 - Note: Virtual source, backed by Lua math.random(), 16 bits available per clock cycle * Zicfilp: Control Flow Integrity - Landing Pad |