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| author | cheapie <cheapiephp@gmail.com> | 2026-10-31 09:50:12 -0500 |
|---|---|---|
| committer | cheapie <cheapiephp@gmail.com> | 2026-10-31 09:50:12 -0500 |
| commit | 78a0395359778eb1a24fdd9332e7fafa041746c5 (patch) | |
| tree | a204614d9b7a15244288268d4dcb147a333373fd /doc/_start_here.txt | |
| parent | b12ac8698b60c00f618bbdf3527570ff91b37f49 (diff) | |
| download | rvcontroller-78a0395359778eb1a24fdd9332e7fafa041746c5.tar rvcontroller-78a0395359778eb1a24fdd9332e7fafa041746c5.tar.gz rvcontroller-78a0395359778eb1a24fdd9332e7fafa041746c5.tar.bz2 rvcontroller-78a0395359778eb1a24fdd9332e7fafa041746c5.tar.xz rvcontroller-78a0395359778eb1a24fdd9332e7fafa041746c5.zip | |
Improve ISA string documentation
Diffstat (limited to 'doc/_start_here.txt')
| -rw-r--r-- | doc/_start_here.txt | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/doc/_start_here.txt b/doc/_start_here.txt index 416eab5..de41840 100644 --- a/doc/_start_here.txt +++ b/doc/_start_here.txt @@ -5,7 +5,7 @@ RVController is a program for use in Luacontrollers (from the mesecons mod) in L It emulates a single RISC-V hart and a configurable amount (64KiB default) of RAM. Features: -* RV32IMACBZicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbkb_Zbkx_Xh3bextm instruction set provides: +* RV32IMACBZicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbkb_Zbkx_Xh3bextm_Xh3misa instruction set provides: - 32-bit address space - 32 32-bit registers (31 general-purpose + 1 zero register) - Selectable endianness @@ -21,6 +21,7 @@ Features: - Single-instruction function prologues/epilogues and jump tables - Compatibility with future MOP-based extensions - Forward-edge control-flow integrity via landing pads + - Compatibility with most code (not involving I/O) written for the WCH CH32V003, Espressif ESP32-C2/C3/C5/C6/C61/H2, Renesas R9A02G020/R9A02G021/R9A06G150, the RISC-V cores of the Raspberry Pi Pico 2, and many other chips * Mutable ISA via writable bits in misa CSR * Mesecons and digilines I/O * Configurable RAM size and clock speed |