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| author | cheapie <cheapiephp@gmail.com> | 2026-06-26 23:34:38 -0500 |
|---|---|---|
| committer | cheapie <cheapiephp@gmail.com> | 2026-06-26 23:34:38 -0500 |
| commit | 338a12a1382afebc6c82e0b40768d87bcab3d8d1 (patch) | |
| tree | 445a6dc22c2c9ddb99b0f831d68fb1999f0ceebc /doc/_start_here.txt | |
| parent | 3a46ab5b8691e72098e3c43f5e25ca84385a5de6 (diff) | |
| download | rvcontroller-338a12a1382afebc6c82e0b40768d87bcab3d8d1.tar rvcontroller-338a12a1382afebc6c82e0b40768d87bcab3d8d1.tar.gz rvcontroller-338a12a1382afebc6c82e0b40768d87bcab3d8d1.tar.bz2 rvcontroller-338a12a1382afebc6c82e0b40768d87bcab3d8d1.tar.xz rvcontroller-338a12a1382afebc6c82e0b40768d87bcab3d8d1.zip | |
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| -rw-r--r-- | doc/_start_here.txt | 88 |
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diff --git a/doc/_start_here.txt b/doc/_start_here.txt new file mode 100644 index 0000000..18a05ac --- /dev/null +++ b/doc/_start_here.txt @@ -0,0 +1,88 @@ +RVController +============ + +RVController is a program for use in Luacontrollers (from the mesecons mod) in Luanti. +It emulates a single RISC-V hart and a configurable amount (64KiB default) of RAM. + +Features: +* RV32IMACBZicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbkb_Zbkx_Xh3bextm instruction set provides: + - 32-bit address space + - 32 32-bit registers (31 general-purpose + 1 zero register) + - Selectable endianness + - Multiply/divide instructions + - Bit manipulation including crossbar permutation and multiple-bit extraction + - Atomic memory operations via load-reserved/store-conditional, compare-and-swap, or math/bitwise operations directly on memory + - Byte/halfword/word atomic memory operation sizes + - Conditional zero instructions + - Freely mixable 16/32-bit instruction lengths + - Performance counters and timers + - Pause hint for power management + - Wait-for-reservation-set instructions to watch for memory changes + - Single-instruction function prologues/epilogues and jump tables + - Compatibility with future MOP-based extensions + - Forward-edge control-flow integrity via landing pads +* Mutable ISA via writable bits in misa CSR +* Mesecons and digilines I/O +* Configurable RAM size and clock speed +* Mesecons, digilines, and timer interrupts +* Support for the privileged architecture (currently M-mode only), including: + - Configurable interrupt masking + - Built-in trap handler, or replace it with your own + - Optional vectored interrupt routing + - Double-trap detection +* Built in machine-code monitor with help system and basic debugging support (including breakpoint) + +Specifications: +RVController is intended to be compliant with the following specifications: +* RV32I Base Integer Instruction Set, Version 2.1 +* "Zifencei" Extension for Instruction-Fetch Fence, Version 2.0 + - Note: Implemented as a 'nop' instruction as memory is always consistent (see note on RVWMO below) +* "Zicsr" Extension for Control and Status Register (CSR) Instructions, Version 2.0 +* "Zicond" Extension for Integer Conditional Operations, Version 1.0.0 +* "Zicntr" Extension for Counters, Version 2.0 +* "Zimop" Extension for May-Be-Operations, Version 1.0 +* "M" Extension for Integer Multiplication and Division, Version 2.0 + - Note: This implies the following: + - * Zmmul Extension, Version 1.0 +* "A" Extension for Atomic Instructions, Version 2.1 + - Note: This implies the following: + - * "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions + - * "Zaamo" Extension for Atomic Memory Operations +* RVWMO Memory Consistency Model, Version 2.0 + - Note: The actual implemented memory model is significantly more strict (memory is always consistent, there is no cache) +* "Ztso" Extension for Total Store Ordering, Version 1.0 +* "C" Extension for Compressed Instructions, Version 2.0 + - Note: This implies the following: + - * "Zca" Extension for Code Size Reduction, Version 1.0.0 +* Zcb: Extension for Code Size Reduction, Version 1.0.0 +* "Zcmop" Compressed May-Be-Operations Extension, Version 1.0 +* Zcmp: Extension for Code Size Reduction, Version 1.0.0 +* Zcmt: Extension for Code Size Reduction, Version 1.0.0 +* "B" Extension for Bit Manipulation, Version 1.0.0 + - Note: This implies the following: + - * Zba: Extension for Address generation, Version 1.0.0 + - * Zbb: Extension for Basic bit-manipulation, Version 1.0.0 + - * Zbs: Extension for Single-bit instructions, Version 1.0.0 +* "Zihintpause" Extension for Pause Hint, Version 2.0 +* Zilsd, Zclsd: Extensions for Load/Store pair for RV32, Version 1.0 +* "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 +* "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 +* "Zalasr" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 +* "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01 +* Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0 +* Zbkx: Extension for Crossbar permutations, Version 1.0.0 +* Zicfilp: Control Flow Integrity - Landing Pad +* Xh3bextm: Hazard3 bit extract multiple + - Note: Defined in the Hazard3 reference manual, available at https://github.com/Wren6991/Hazard3/releases/download/v1.1/hazard3.pdf +* Machine-Level ISA, Version 1.13 +* "Smdbltrp" Double Trap Extension, Version 1.0 + +For full specification text, visit https://docs.riscv.org/reference/home/index.html + +Documentation files: +* _start_here.txt: This file +* toolchain.txt: Cross-toolchain setup, needed if you want to build software and don't already have a riscv32(be)-none-elf toolchain +* monitor.txt: Setup and operation of the built-in machine-code monitor +* ecall.txt: Available M-mode ecall functions +* csr.txt: Control and status registers +* mmio.txt: Memory-mapped I/O |