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| author | Christopher Head <chead@chead.ca> | 2018-12-09 05:38:23 -0800 |
|---|---|---|
| committer | Vitaliy <numzer0@yandex.ru> | 2018-12-09 16:38:23 +0300 |
| commit | 9d239cbfff5db2780dacd0d67479eed194ec340d (patch) | |
| tree | 75932a36589d50e6bcbeda3c1f4b930e336823e7 /mesecons_fpga | |
| parent | d3cabedbb08d4edb632fbbec77fb0ae0fd680379 (diff) | |
| download | mesecons-9d239cbfff5db2780dacd0d67479eed194ec340d.tar mesecons-9d239cbfff5db2780dacd0d67479eed194ec340d.tar.gz mesecons-9d239cbfff5db2780dacd0d67479eed194ec340d.tar.bz2 mesecons-9d239cbfff5db2780dacd0d67479eed194ec340d.tar.xz mesecons-9d239cbfff5db2780dacd0d67479eed194ec340d.zip | |
Fix typos (#442)
Diffstat (limited to 'mesecons_fpga')
| -rw-r--r-- | mesecons_fpga/doc/fpga/description.html | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/mesecons_fpga/doc/fpga/description.html b/mesecons_fpga/doc/fpga/description.html index be6bd65..95177b2 100644 --- a/mesecons_fpga/doc/fpga/description.html +++ b/mesecons_fpga/doc/fpga/description.html @@ -1,5 +1,5 @@ FPGAs can be used to chain multiple logic gates together in a compact manner. They come with 4 I/O ports and 10 internal registers, -which can then be connected with eachother to form logic circuits.<br /> +which can then be connected with each other to form logic circuits.<br /> Supported gate types: <b>AND</b>, <b>OR</b>, <b>NOT</b>, <b>XOR</b>, <b>NAND</b>, <b>XNOR</b>, <b>Buffer</b> (=)<br /> I/O ports: <b>A B C D</b>; Registers: numbered <b>0</b> to <b>9</b> |