From b6ecc5f2f1c6aa350b2fdb4d73b6bd410bdab951 Mon Sep 17 00:00:00 2001 From: cheapie Date: Sat, 7 Nov 2026 05:45:09 -0600 Subject: Add Zbc (and by extension, Zbkc) --- doc/_start_here.txt | 7 +++++-- doc/instructions.txt | 8 ++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'doc') diff --git a/doc/_start_here.txt b/doc/_start_here.txt index 125de5f..745f83a 100644 --- a/doc/_start_here.txt +++ b/doc/_start_here.txt @@ -5,12 +5,12 @@ RVController is a program for use in Luacontrollers (from the mesecons mod) in L It emulates a single RISC-V hart and a configurable amount (64KiB default) of RAM. Features: -* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbkb_Zbkx_Xh3bextm_Xh3misa instruction set provides: +* RV32IMACBZicboz_Zicfilp_Zicntr_Zicond_Zicsr_Zifencei_Zihintpause_Zihpm_Zilsd_Zimop_Zabha_Zacas_Zalasr_Zawrs_Zcb_Zclsd_Zcmop_Zcmp_Zcmt_Zbc_Zbkb_Zbkc_Zbkx_Xh3bextm_Xh3misa instruction set provides: - 32-bit address space - 32 32-bit registers (31 general-purpose + 1 zero register) - Selectable endianness - Multiply/divide instructions - - Bit manipulation including crossbar permutation and multiple-bit extraction + - Bit manipulation including crossbar permutation, multiple-bit extraction, and carry-less multiplication - Atomic memory operations via load-reserved/store-conditional, compare-and-swap, or math/bitwise operations directly on memory - Byte/halfword/word atomic memory operation sizes - Conditional zero instructions @@ -66,6 +66,9 @@ RVController is intended to be compliant with the following specifications: - * Zba: Extension for Address generation, Version 1.0.0 - * Zbb: Extension for Basic bit-manipulation, Version 1.0.0 - * Zbs: Extension for Single-bit instructions, Version 1.0.0 +* Zbc: Extension for Carry-less multiplication, Version 1.0.0 + - Note: This implies the following: + - * Zbkc: Extension for Carry-less multiplication for Cryptography, Version 1.0.0 * "Zihintpause" Extension for Pause Hint, Version 2.0 * Zilsd, Zclsd: Extensions for Load/Store pair for RV32, Version 1.0 * "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 diff --git a/doc/instructions.txt b/doc/instructions.txt index 149d3c5..524a2b8 100644 --- a/doc/instructions.txt +++ b/doc/instructions.txt @@ -70,6 +70,9 @@ RV32I Base Integer Instruction Set, Version 2.1: * amomin.w rd,rs1,rs2 | Atomic integer minimum(memory,register), word size * amominu.w rd,rs1,rs2 | Atomic integer minimum(memory,register) (unsigned), word size +"CMO" Extensions for Base Cache Management Operation ISA, Version 1.0.0 +* cbo.zero 0(rs1) | Cache block zero + "C" Extension for Compressed Instructions, Version 2.0 * c.lwsp rd,imm | Compressed load word, stack pointer relative * c.swsp rs2,imm | Compressed store word, stack pointer relative @@ -129,6 +132,11 @@ RV32I Base Integer Instruction Set, Version 2.1: * bset rd,rs1,rs2 | Single-bit set (by register) * bseti rd,rs1,rs2 | Single-bit set (by immediate) +Zbc: Extension for Carry-less multiplication, Version 1.0.0 +* clmul rd,rs1,rs2 | Carry-less multiply (low part) +* clmulh rd,rs1,rs2 | Carry-less multiply (high part) +* clmulr rd,rs1,rs2 | Carry-less multiply (reversed) + Zicfilp: Control Flow Integrity - Landing Pad: * lpad imm | Landing pad -- cgit v1.2.3