From 71729845170cdb4380f1ae42708638fdaee997cb Mon Sep 17 00:00:00 2001 From: cheapie Date: Sun, 8 Nov 2026 06:45:52 -0600 Subject: Add Smcntrpmf --- doc/_start_here.txt | 1 + doc/csr.txt | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'doc') diff --git a/doc/_start_here.txt b/doc/_start_here.txt index b2693d1..b9dc6d0 100644 --- a/doc/_start_here.txt +++ b/doc/_start_here.txt @@ -88,6 +88,7 @@ RVController is intended to be compliant with the following specifications: * Xh3bextm: Hazard3 bit extract multiple, Version 1.0 - Note: Defined in the Hazard3 reference manual, available at https://github.com/Wren6991/Hazard3/releases/download/v1.1/hazard3.pdf * Machine-Level ISA, Version 1.13 +* "Smcntrpmf" Cycle and Instret Privilege Mode Filtering, Version 1.0 * "Smdbltrp" Double Trap Extension, Version 1.0 For full specification text, visit https://docs.riscv.org/reference/home/index.html diff --git a/doc/csr.txt b/doc/csr.txt index 866f2e3..2e88f67 100644 --- a/doc/csr.txt +++ b/doc/csr.txt @@ -10,6 +10,8 @@ The following standard CSRs are available: * 0x305: mtvec * 0x310: mstatush * 0x320: mcountinhibit +* 0x321: mcyclecfg +* 0x322: minstretcfg * 0x323 - 0x33f: mhpmevent3 - mhpmevent31 * 0x340: mscratch * 0x341: mepc @@ -17,6 +19,8 @@ The following standard CSRs are available: * 0x343: mtval * 0x344: mip * 0x34b: mtval2 +* 0x721: mcyclecfgh +* 0x722: minstretcfgh * 0x747: mseccfg * 0xb00: mcycle * 0xb02: minstret -- cgit v1.2.3