From 747374b7e56717d39d6f5dbef7e1c04cbf0c5355 Mon Sep 17 00:00:00 2001 From: cheapie Date: Thu, 5 Nov 2026 05:02:41 -0600 Subject: More work on rrxing2 --- assembly/rrxing2/rrxing2.S | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'assembly/rrxing2/rrxing2.S') diff --git a/assembly/rrxing2/rrxing2.S b/assembly/rrxing2/rrxing2.S index 2118ca1..4501948 100644 --- a/assembly/rrxing2/rrxing2.S +++ b/assembly/rrxing2/rrxing2.S @@ -3,6 +3,8 @@ j _start .include "util.S" _start: +li t0,0x400 +csrs mseccfg,t0 # Turn on MLPE (enable Zicfilp) li sp,0x10000 # Set up stack pointer la t0,handler csrw mtvec,t0 # Set up trap handler @@ -30,7 +32,7 @@ digiline_send signalchannel,lightredmsg .align 2 handler: -csrrw x31,mscratch,x31 # Free up x31 to hold the context address +csrw mscratch,x31 # Free up x31 to hold the context address la x31,hcontext # Using x register numbers here since trap handlers don't use the usual calling convention sw x1,0(x31) # Save all the registers to the context sd x2,4(x31) # Two at a time since we have Zilsd/Zclsd @@ -51,9 +53,6 @@ sw x30,116(x31) csrr x30,mscratch # Get the old x31 value back into a register sw x30,120(x31) # and write that back out too -li t0,0x400 -csrw mseccfg,t0 # Turn on MLPE (enable Zicfilp) - csrr t0,mcause # Read why the trap occurred li t1,0x80000011 # Interrupt 17 = digilines -- cgit v1.2.3