diff options
Diffstat (limited to 'rvcontroller.lua')
| -rw-r--r-- | rvcontroller.lua | 145 |
1 files changed, 145 insertions, 0 deletions
diff --git a/rvcontroller.lua b/rvcontroller.lua index ef1985f..13e4c24 100644 --- a/rvcontroller.lua +++ b/rvcontroller.lua @@ -419,6 +419,137 @@ local function readcsr(address) local bits = {} bits[10] = mem.mlpe return implodebits(bits,32) + elseif address == 0xbf1 and mem.isa.x then --h3.misa + local page = mem.csr[0xbf1] + if page == 0 then + local bits = { + [0] = mem.isa.a, --A + mem.isa.b, --B + mem.isa.c, --C + false, --D + not mem.isa.i, --E + false, --F + false, --Reserved + false, --H + mem.isa.i, --I + false, --Reserved + false, --Reserved + false, --Reserved + mem.isa.m, --M + false, --Reserved + false, --Reserved + false, --Reserved + false, --Q + false, --Reserved + false, --Reserved + false, --Reserved + false, --Reserved + false, --V + false, --Reserved + false, --Reserved + false, --Reserved + false, --Reserved + mem.isa.a, --Zacas + mem.isa.b, --Zba + mem.isa.b, --Zbb + false, --Zbc + mem.isa.b, --Zbkb + false, --Zbkc + } + return implodebits(bits,32) + elseif page == 1 then + local bits = { + [0] = mem.isa.b, --Zbkx + mem.isa.b, --Zbs + false, --Zfa + false, --Zfh + false, --Zfhmin + false, --Zicboz + true, --Zicond + false, --Zihintntl + true, --Zihintpause + false, --Zknd + false, --Zkne + false, --Zknh + false, --Zksed + false, --Zksh + true, --Zkt + true, --Ztso + false, --Zvbb + false, --Zvbc + false, --Zvfh + false, --Zvfhmin + false, --Zvkb + false, --Zvkg + false, --Zvkned + false, --Zvknha + false, --Zvknhb + false, --Zvksed + false, --Zvksh + false, --Zvkt + false, --Zve32x + false, --Zve32f + false, --Zve64x + false, --Zve64f + } + return implodebits(bits,32) + elseif page == 2 then + local bits = { + [0] = false, --Zve64d + true, --Zimop + mem.isa.c, --Zca + mem.isa.c, --Zcb + false, --Zcd + false, --Zcf + mem.isa.c, --Zcmop + mem.isa.a, --Zawrs + true, --Zilsd + mem.isa.c, --Zclsd + mem.isa.c, --Zcmp + true, --Zifencei + mem.isa.m, --Zmmul + false, --Zibi + false, --supm(?) + true, --Zicntr + false, --Zihpm + false, --Zfbfmin + false, --Zvfbfmin + false, --Zvfbfwma + false, --Zicbom + mem.isa.a, --Zaamo + mem.isa.a, --Zalrsc + mem.isa.a, --Zabha + mem.isa.a, --Zalasr + false, --Zicbop + true, --Zicfilp + false, --Zicfiss + } + return implodebits(bits,32) + elseif page == 0x400 then + --Standard extension list length + return 92 + elseif page == 0x401 then + --Hazard3 custom extension list length + return 5 + elseif page == 0x500 then + --Xh3misa version 1.0 + return 0x01010000 + elseif page == 0x501 then + --Xh3irq not supported + return 0 + elseif page == 0x502 then + --Xh3pmpm not supported + return 0 + elseif page == 0x503 then + --Xh3power not supported + return 0 + elseif page == 0x504 then + --Xh3bextm version 1.0 + return 0x01010000 + else + --Unknown page, whatever is being asked about isn't supported + return 0 + end elseif not mem.csr[address] then digiline_send("monitordisp",string.format("Attempted read\nfrom unknown\nCSR 0x%03X\nPC: %08X",address,mem.registers.pc)) fault = 2 @@ -1015,6 +1146,12 @@ local operations = { return trap(3,0) end, csrrw = function(rd,rs1,imm) + if imm == 0xbf1 and mem.isa.x then + --h3.misa needs the write to happen first + writecsr(imm,getreg(rs1)) + setreg(rd,readcsr(imm)) + return checkinterrupts() + end local out = readcsr(imm) writecsr(imm,getreg(rs1)) setreg(rd,out) @@ -1051,6 +1188,12 @@ local operations = { return checkinterrupts() end, csrrwi = function(rd,rs1,imm) + if imm == 0xbf1 and mem.isa.x then + --h3.misa needs the write to happen first + writecsr(imm,rs1) + setreg(rd,readcsr(imm)) + return checkinterrupts() + end setreg(rd,readcsr(imm)) writecsr(imm,rs1) return checkinterrupts() @@ -2789,6 +2932,7 @@ local csraliases = { mcycleh = 0xb80, minstreth = 0xb82, mseccfg = 0x747, + ["h3.misa"] = 0xbf1, } if event.type == "program" or event.iid == "reset" then @@ -2822,6 +2966,7 @@ if event.type == "program" or event.iid == "reset" then [0x34b] = 0, --mtval2 [0x800] = 0, --Clock Controls [0x801] = 0, --MMIO Base Address + [0xbf1] = 0, --h3.misa [0xc00] = 0, --CYCLE [0xc01] = 0, --TIME [0xc02] = 0, --INSTRET |